An apparatus includes a central processing unit having an output to provide a status indicator, a graphics controller having an output coupleable to a display interface, a cache comprising a plurality of cache lines, and memory controller having an input to receive the status indicator. The memory controller is configured to disable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central processing unit is in an active mode. The memory controller further is configured to enable allocation of cache lines of the cache for cache misses for data requests from the graphics controller in response to the status indicator indicating the central processing unit is in an idle mode.
