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Programmable in-situ delay fault test clock generator
 
   
Document Number
US Patent 7536617
Issued Date
May 19, 2009
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Inventors
Kim; Heong (San Jose, CA)
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Abstract
A system and method for programmable in-situ launch and capture clock generation is provided. The system provides an efficient and improved manner for delay and signal transition fault testing in electronic circuits. The system comprises i) an in-situ delay clock generator for generating one or more clocks; ii) a pulse Programmable Selection Generator (PSG) which can be either a pulse PSG and/or an expanded pulse PSG for generating the sequence in which the clocks are to be selected, the clocks being selected with a delay; and iii) a multiplexer for selecting the plurality of clocks, based on the generated sequence, the selected clocks being used for generating the launch and capture clocks.
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Number of Claims:
17
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Owner
Cisco Technology, Inc. (San Jose, CA)
Published
May 19, 2009
Application Number
11/103,877
Filed
April 12, 2005
US Classification
714/731   327/116 327/141 327/158
Int'l Classification
G01R   31/28   (20060101)  
Examiner
Assistant Examiner
Attorney/Law Firm
USPTO Field of Search
714/731  
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