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System and method for packet processor status monitoring
   
Document Number
US Patent 7539750
Issued Date
May 26, 2009
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Abstract
Disclosed herein are a system and method for status monitoring, including debug error detection, during data packet processing. In general terms, the system for status monitoring during data packet processing can be implemented as a system including a packet processor and a buffer. The packet processor generates processing data based on one or more control structures while revising packet data. The packet processor generates the processing data while performing one or more lookup cycles. The buffer records the processing data and the status of the one or more control structures. The processing data includes a lookup number and the lookup number identifies the number of cycles performed by the packet processor.
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Number of Claims:
71
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Owner
Extreme Networks, Inc. (Santa Clara, CA)
Published
May 26, 2009
Application Number
10/814,728
Filed
March 30, 2004
US Classification
709/224   709/232
Int'l Classification
G06F   15/16   (20060101)   G06F   12/00   (20060101)  
Examiner
Attorney/Law Firm
USPTO Field of Search
709/224   709/232  
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