An improved approach to cache management is disclosed which may be implemented to provide fine-grained control over individual caches or subsets of a multi-level cache hierarchy. By selectively operating on shared and unshared caches during power management processing, more efficient system operation can be achieved. In one example, a microprocessor is adapted to interface with multiple caches configured in multiple cache levels. The microprocessor includes multiple processors associated with the caches. At least one of the processors is adapted to execute an instruction configured to identify a subset of the caches. The microprocessor also includes a control circuit adapted to perform an operation on the subset of the caches in response to an execution of the instruction by the at least one of the processors.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Patent Application No. 60/731,784 filed on Oct. 31, 2005 and entitled "Extended cache operations to provide control over which levels of the hierarchy they apply to" which is incorporated herein by reference.
