or
Bookmark and Share
Method and apparatus for isolating bus failure
 
   
Document Number
US Patent 7543191
Issued Date
June 2, 2009
Link
Inventors
Map
Abstract
The embodiments of the present invention disclose a method for isolating a bus failure, which includes: acquiring, from a Compact PCI bus, an address of a target board being accessed; counting retry responses on the Compact PCI bus, wherein the retry responses are generated by access to the target board; sending a reset signal to the target board in response to that the times of the retry responses exceed a retry times threshold. With the embodiments of this invention, the normal operation of a failed device in the system may be restored in time, which may avoid that the bus is hanged up and is favorable for maintenance.
Tags:
Description:
Amusing 0%
Clever 0%
Complex 0%
Efficient 0%
Historic 0%
Important 0%
Innovative 0%
Interesting 0%
Practical 0%
Simple 0%
Number of Claims:
16
Comments:
no comments yet
Owner
Published
June 2, 2009
Application Number
11/843,452
Filed
August 22, 2007
US Classification
714/43   710/100 714/56
Int'l Classification
G06F   11/00   (20060101)  
Assistant Examiner
Attorney/Law Firm
Priority Data
Sep 29, 2006 [CN] 2006 1 0062954
USPTO Field of Search
714/43   714/56  
Related Patents
Claims
Description
About| FAQs| Terms & Disclaimer| Link to Us| Contact Us