or
Bookmark and Share
Method for testing semiconductor integrated circuit and method for verifying design rules
 
   
Document Number
US Patent 7543206
Issued Date
June 2, 2009
Link
Inventors
Map
Abstract
A method is provided for testing a semiconductor integrated circuit by utilizing a scan path circuit provided to detect the degeneracy fault in the semiconductor integrated circuit, and bringing scan chains to states in which shift resistor operations can be effected for the input of patterns by which a glitch fault and the IR-DROP fault between the scan chains can be detected.
Tags:
Description:
Amusing 0%
Clever 0%
Complex 0%
Efficient 0%
Historic 0%
Important 0%
Innovative 0%
Interesting 0%
Practical 0%
Simple 0%
Number of Claims:
9
Comments:
no comments yet
Owner
Published
June 2, 2009
Application Number
11/445,195
Filed
June 2, 2006
US Classification
714/726  
Int'l Classification
G01R   31/26   (20060101)  
Attorney/Law Firm
Priority Data
Nov 18, 2005 [JP] 2005-334437
USPTO Field of Search
714/726  
Related Patents
Claims
Description
About| FAQs| Terms & Disclaimer| Link to Us| Contact Us