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Method and apparatus for debugging semiconductor devices
 
   
Document Number
US Patent 7546507
Issued Date
June 9, 2009
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Inventors
Reilly; Daniel (Mountain View, CA)
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Abstract
A tool for testing an integrated circuit is provided. The tool includes a vector execution engine, a vector image generation engine and a vector display engine. The vector execution engine applies test patterns to the integrated circuit and captures error data being output from the test patterns. The vector image generation engine generates a file of expected output from the application of the test patterns to the integrated circuit. It should be appreciated that the generation of the vector image file occurs offline from the testing by the vector execution engine. The tool also includes a vector display engine allowing identification of vectors including error data. In one embodiment, a timestamp is associated with the vectors of the vector image file and a timestamp is associated with the vectors of the error data. A method for testing an integrated circuit and a graphical user interface are also included.
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Number of Claims:
22
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Owner
Altera Corporation (San Jose, CA)
Published
June 9, 2009
Application Number
11/292,494
Filed
December 2, 2005
US Classification
714/742  
Int'l Classification
G01R   31/28   (20060101)   G06F   11/00   (20060101)  
USPTO Field of Search
714/42  
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