This invention relates to a circuit technique for rapidly and efficiently correcting for read and write data errors in a digital semiconductor memory. More generally, this can also be in any type of digital memory or digital communication channel. As semiconductor memories get smaller and smaller, the memory cells are subject to higher rates of manufacturing defects and soft errors. Correction of manufacturing defects is achieved through extensive testing and use of redundant memory cells to replace defective memory cells. Soft errors are very difficult to detect and correct and only the simplest parity check codes have been implemented. The cost in terms of delay time and computational complexity are barriers to the implementation of ECC. This invention represents a device that introduces very little delay and requires minimal hardware complexity to implement.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of the filing date of U.S. Provisional Application Ser. No. 60/598,392 entitled "error-correcting circuit for high-density memory," and filed on Aug. 3, 2004 by inventors Elaine Ou and Woodward Yang.
