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High-speed PCI interface system and a reset method thereof
   
Document Number
US Patent 7549009
Issued Date
June 16, 2009
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Abstract
A high-speed PCI interface system with reset function and a reset method thereof are provided. The interface system comprises a host controller chipset, at least one high-speed PCI device and at least one reset signal generator. While a hot reset packet cannot be executed by the high-speed PCI device, the host controller chipset can respectively transmit a trigger signal and a PCI reset signal to each corresponding reset signal generator through a trigger signal line and a PCI reset signal line, and further the reset signal generator operates to generate a basic resetting signal. Finally, the basic resetting signal will be transmitted to the corresponding high-speed PCI device through a basic reset signal line such that the system can be used to operate the basic resetting action without restarting power.
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Number of Claims:
20
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Owner
Published
June 16, 2009
Application Number
11/619,047
Filed
January 2, 2007
US Classification
710/313   710/107
Int'l Classification
G06F   13/00   (20060101)  
Examiner
Attorney/Law Firm
Priority Data
Jan 02, 2006 [TW] 95100104 A
USPTO Field of Search
710/107   710/305   710/313  
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