A testing apparatus includes a logic comparing unit for comparing the output value with a predetermined expectation value; a pass/fail determining module for determining pass/fail of the device under test based on the comparison result of the logic comparing unit; and a clock generating circuit including a first phase comparing unit for comparing phase of the output data of the device under test with that of the reproduced clock and outputting a first comparison result signal; a second phase comparing unit for comparing phase of the reference clock with that of the reproduced clock and outputting a second comparison result signal; and a reproduced clock generating module for generating the reproduced clock based on the first and second comparison result signals.
The present application is a continuation application of PCT/JP2005/004370 filed on Mar. 11, 2005, claiming priority from a Japanese patent application No. 2004-93310 filed on Mar. 26, 2004, the contents of which are incorporated herein by reference.
