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Select transistor using buried bit line from core
   
Document Number
US Patent 7561457
Issued Date
July 14, 2009
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Inventors
He; Yi (Fremont, CA)
Sinha; Shankar (Redwood Shores, CA)
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Abstract
A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in the core memory array and with substantially the same channel length.
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Number of Claims:
17
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Owner
Spansion LLC (Sunnyvale, CA)
Published
July 14, 2009
Application Number
11/465,701
Filed
August 18, 2006
US Classification
365/104   365/129 365/185.26 365/63
Int'l Classification
G11C   17/00   (20060101)  
Examiner
Attorney/Law Firm
USPTO Field of Search
365/104   365/185.26   365/63   365/129  
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