Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.
CROSS REFERENCES TO RELATED APPLICATIONS
This is a divisional of U.S. patent application Ser. No. 10/722,159, filed 26 Nov. 2003 now U.S. Pat. No. 7,148,563, the contents of which are incorporated herein by reference in their entirety, and also claims the priority benefit under 35 U.S.C. .sctn. 119 from Korean Patent Application No. 2002-75805, filed on Dec. 2, 2002, the contents of which are also incorporated herein by reference in their entirety.
