In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.
CROSS REFERENCE
This patent application claims priority to and incorporates by reference the U.S. Provisional Application, Ser. No. 60/533,280, entitled "Programmable Logic Device with Cascading DSP Slices", by James M. Simkins, et al., filed Dec. 29, 2003 and U.S. Provisional Application Ser. No. 60/608,724, entitled "Applications of Cascading DSP Slices", by James M. Simkins et al. filed Sep. 9, 2004.
