An array substrate, a gate insulating layer, and a data line are deposited sequentially on a liquid crystal cell. At a part of this configuration, a planarizing layer covers the gate insulating layer and the data line. The planarizing layer has a groove formed right above the data line. A common electrode is formed on internal walls of the groove and on the flat surface of the planarizing layer corresponding to the shoulders of the groove. A pixel electrode is formed on the flat surface with a certain distance from the common electrode.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a divisional application of U.S. application Ser. No. 10/732,489 filed Dec. 11, 2003, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2002-368854 filed on Dec. 19, 2002, the entire contents of which are incorporated herein by reference.
