A display panel includes a plurality of sets of transistors which are formed on an upper side of a substrate. An insulating film is formed to cover upper surfaces of the transistors and has a plurality of trenches formed in an upper surface thereof. A plurality of first interconnections are buried in the trenches. An interconnection insulating film covers upper surfaces of the first interconnections. A plurality of second interconnections are provided on an upper side of the interconnection insulating film. Each of a plurality of pixel electrodes is provided between two adjacent interconnections of the second interconnections. Each of a plurality of light-emitting layers is provided on one of the pixel electrodes. A counter electrode is provided on the light-emitting layers.
