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Mechanisms to prevent undesirable bus behavior
   
Document Number
US Patent 7577877
Issued Date
August 18, 2009
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Abstract
A system includes proxy logic which detects situations which, unless action is taken, would result in undesirable bus behavior. In one embodiment, the target device of a bus cycle includes proxy logic which determines when the target device is unable to respond correctly to a bus cycle. In this situation, the proxy logic blocks a bus signal from being received by the addressed logic in the target device, thereby preventing the target device from responding at all. In another embodiment, proxy logic is located external to the target device and determines when the target device has not responded to a cycle intended for it. When this condition has occurred, the proxy logic responds to the cycle before the bus's subtractive decode agent has a chance to claim the cycle. The proxy logic's response may be to return bogus data or terminate or abort the cycle.
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Number of Claims:
30
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Published
August 18, 2009
Application Number
10/444,154
Filed
May 22, 2003
US Classification
714/43   710/15 710/17 710/18 714/44
Int'l Classification
G06F   11/00   (20060101)  
USPTO Field of Search
714/43  
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