A solid-state image sensor device having an image sensing portion performing the photoelectric conversion and being able to correspond to both progressive mode in which all picture element signals obtained by the scanning of one time are output independently, and interlaced mode in which a plurality of interlaced scannings are performed and the picture element signals obtained by respective interlaced scannings are superposed, comprises a substrate-bias generation circuit for applying a bias voltage to the substrate of the image sensing portion, and for controlling the value of the bias voltage in the progressive mode to be smaller in comparison with that in the interlaced mode.
The subject matter of application Ser. No. 09/324,823 is incorporated herein by reference. The present application is a continuation of U.S. application Ser. No. 09/324,823, filed Jun. 2, 1999, now U.S. Pat. No. 7,315,328 which claims priority to Japanese Patent Application No. JP 10-152434, filed Jun. 2, 1998. The present application claims priority to these previously filed applications.
