An apparatus for encoding a plurality of image data series and decoding a plurality of encoded image data series includes an interface control circuit for executing data read/write operation from and to a memory area, an encoding/decoding circuit for selectively executing encoding of image data of one series written into the memory area or decoding of encoded image data of one series, and a plurality of registers for giving an instruction of processing to the encoding/decoding circuit wherein the encoding/decoding circuit executes encoding and decoding on a time division basis and in a series unit for image data of a plurality of series in accordance with the instruction from the plurality of registers. The apparatus for executing encoding and decoding of multi-stream image data can be rendered compact in size.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a Continuation of application Ser. No. 11/008,178 filed Dec. 10, 2004 now U.S. Pat. No. 7,412,101. Priority is claimed based on U.S. application Ser. No. 11/008,178 filed Dec. 10, 2004, which claims the priority Japanese Application No. 2003-414284, filed on Dec. 12, 2003, all of which is incorporated by reference.
