Various methods and apparatuses are described for a system that includes some on-chip components, e.g., I-Os, test processors, soft wrappers, etc., an external testing unit that provides Parametric Measurement Unit (PMU) capability, and various tests performed on the I-Os by the on-chip testing logic, the test vector patterns supplied by the external testing unit.
RELATED APPLICATIONS
This application claims priority to U.S. Provisional Patent Application No. 60/716,386, entitled VARI-OUS METHODS AND APPARATUSES FOR INPUT-OUTPUT DESIGNS, filed on Sep. 12, 2005.
