A logic gate has a fault sensing circuit connected to each of its input terminals and connected to actuate a switching means that open circuits the gate output terminal when there is no current flow either into or out of each gate input terminal. A first embodiment includes a photosensitive type current sensing circuit connected to the input terminal of a NOT gate. When a fault occurs at this terminal, a switching transistor actuates to turn off two drive transistors in a buffer circuit, which open circuits the output terminal. A second embodiment is similar but includes a transistor type current sensing circuit connected to the input terminal of a NOT gate. A third embodiment includes two fault sensing circuits connected to each of two input terminals of a NAND gate. Each fault sensing circuit connects to turn off the two drive transistors in a buffer circuit when a fault occurs at either input terminal. And finally, a fourth embodiment includes a fault sensing circuit connected to each of two input terminals of an AND gate, each circuit connected to deenergize a relay coil which opens a switch in the gate output terminal when a fault occurs at either input terminal.
A novel sense amplifier circuit providing conversion of MOS input signals to TTL output signals with tri-state logic output at the output data bus, the input circuit of the sense amplifier providing current sensing and programmable input thresholds for economical construction and enhanced speed of operation of the sense amplifier. A novel tri-state operation is provided for the input section of the sense amplifier to provide either a clamped voltage at the input data bus line during MOS to TTL communication or a floating input when it is desired that MOS devices on the input data bus are to communicate.
A circuit and method for detecting and protecting against an overcurrent condition in a power transistor switching device, and particularly an IGBT. The power transistor switching device has main terminals and a control terminal, the main terminal having a normal saturation voltage therebetween during normal conduction of the power transistor device. The circuit includes a driver providing control signals to the control terminal of the power transistor device for switching the power transistor device on and off, a sensing circuit coupled to the power transistor device for sensing the saturation voltage of the power transistor device, and a switching circuit coupled to the control terminal of the power transistor device and responsive to the sensing circuit for removing the control signals from the control terminal in the event the saturation voltage reaches an abnormal level indicating an overcurrent condition in the power transistor device.
A fail-safe logic circuit which includes a pulse generator driven series arrangement of opto-isolators each of which generates a pulsating signal at its output as a function of the logic level state of its respective input terminal. If all input terminals are logic level highs, then a pulsating output signal is equivalent to a true state whereas either a DC or zero level signal is indicative of a false state.
The state of a sensing device such as a switch is indicated as a logic signal at a circuit output terminal and a malfunction is indicated at another circuit output when the connections to the sensing device open circuit or short circuit. The input circuit employs a pair of LED photo-isolators which conduct during alternate half cycles of an a-c current which is applied through the sensing device when it is closed. A diode connects in shunt with the sensing device and when the device is open, only one of the photo-isolators conducts. If a malfunction occurs, neither photo-isolator conducts.
