A demodulation system is provided in which the pulse-number-modulated binary signals for example "1" and "0" which are represented by the existence and absence of a predetermined number of successive pulses, respectively, are demodulated by use of the charging and discharge of a capacitor. When one of the pulse-number-modulated binary signals, for example "1," is demodulated, the discharge of the charged capacitor is made slower than that of the prior art system, whereas the discharge of the capacitor is made at the high speed when the other pulse-number-modulated binary signal, for example, "0" is demodulated.
A pulse generator, such as in a printing process, outputs pulses which are fed to a first threshold value circuit which generates respective rectangular pulses whose duration depends upon the time the respective pulse exceeds a first threshold value. An initially charged capacitor is discharged at a first rate in response to the leading edge of the rectangular pulse and at a second rate, twice the first rate, in response to the trailing edge of a rectangular pulse. The capacitor is connected to a second threshold value circuit which outputs pulse signals when the potential of the capacitor falls below a second threshold value.
A sampling filter-detector receives input signals of different frequencies and provides an output, or detect signal, only when the input frequency has a predetermined value essentially equal to the drive frequency of the sampling circuit. The input signal is coupled through a series of solid state switches, or multipliers, to storage, or sampling, capacitors, the average voltages of which are coupled through voltage peak and valley followers to a comparator which supplies an output or detect signal only when the difference between the positive and negative voltage inputs to the comparator is greater than a certain value. This occurs when the input frequency is within the detector bandwidth. A threshold voltage of a desired value may be placed in the circuit coupling the peak follower and the positive input of the comparator. The solid state switches are turned on and off by pulses from digital logic means such that the switches are on 120.degree. apart in time for the drive frequency which is equal to the frequency to be detected by the filter detector. The response to the third harmonic of the input signal fundamental is eliminated as are multiples of the third harmonic.
Circuit arrangement for demodulating a voltage which is ASK modulated by alternating the amplitude between a low and a high level. Respective charging voltages are produced on first and second charging circuits, with a decoupling device decoupling the first charging circuit at a prescribed ratio between the charging voltage from the second charging circuit and an input voltage for a rectifier circuit.
An improved sampling filter detector circuit for sampling input signals of different frequencies and providing a detect signal when the input frequency has a desired predetermined value. The circuit is suitable for use as a tone detector for continuous tone control squelch systems. The sampling filter detector substantially eliminates response to low order harmonics of the desired frequency and provides the ability to program the filter detector bandwidth by digital means without altering passive components thereby permitting reverse burst detection.
The present invention receives time of day information from a time code grator which employs Pulse Duration Modulation (PDM) code and decodes it in a manner that is frequency independent and time-lag compensated. According to the present time-code reader, the time-coded input is decoded into peaks (amplitude modulated cycles) carried on a normal sine wave. The number of these cyclical peaks are proportional to the duration of the D. C. pulse of the PDM code and can be counted to determine whether a binary 1 or 0 has been transmitted. Because a peak may be lost or missed due to distortion, the invention reads four to six peaks as a 1 and less than four peaks as a 0. The serially received 1's and 0's are transmitted through a network which takes approximately one second to pass data from input to output display. To compensate for this time lag, one second is added on to the output reading to make it contemporaneous with the input signal. The final output is a display of seconds, minutes, hours, days, and control functions.