A peripheral unit such as a teletypewriter, associated with a data processor but operating at a relatively slow rate so as to require an interruption of the processor's program when transmitting data, communicates with the processor through an interface unit comprising a sequential network switchable from a quiescent state (D) to an active state (C) via a preparatory state (A) and an intermediate state (B). The sequential network assumes its preparatory state (A) upon the appearance, at the interface unit, of an input/output instruction read out from a program store in the processor and addressed to the associated peripheral unit; the changeover to the intermediate state (B) occurs immediately thereafter if that peripheral unit emits a "data ready" signal (s). In the absence of overriding priorities within the processor or from higher-ranking peripheral units, an authorization signal (p) from the processor results in a switchover to the active state (C) commanding a program interruption; a confirmation signal (k) from the processor then restores the quiescent state (D) after causing transmission of the address of the associated peripheral unit to the processor, along with the data available at that unit.

At least one parallel processor (PP or P-P) is connected between a central processing unit (CPU) interface and main memory for processing certain data simultaneously and synchronously with operation of the CPU. Integrated circuit apparatus for implementing the functions performed by the PP includes an arithmetic and logic unit (ALU), a set of registers, microprogrammable circuitry (RAM's, ROM's, PROM's) and other integrated circuitry. The PP includes decode and control apparatus, which decodes microinstructions stored in an extension to the control store of the CPU, the extension forming part of the CPU/P-P interface, and thereafter employs the decoded microinstructions to control operation of the P-P.

An apparatus for transferring data between a computer system having a first architecture and a slave element having a second architecture. The apparatus includes a first connector corresponding to the first architecture, a second connector corresponding to the second architecture, and conversion circuitry located between the first connector and the second connector. The conversion circuitry converts signals corresponding to the first architecture to signals corresponding to the second architecture and signals corresponding to the second architecture to signals corresponding to the first architecture.

A distributed input/output system is disclosed for controlling numerous peripheral devices and the transfer of data signals and control signals between those devices and a general purpose digital computer. The control system described includes a multiplexer which can accommodate as many as eight input/output devices under the control of separate programmable microcoded peripheral-unit controllers. Each controller is adapted to be located at or on an individual peripheral device and each is connected to the multiplexer by an identical ribbon cable that is employed to carry both signals and power. Each controller employs a substantially identical microengine, that is, a microcoded processor, currently of five integrated circuit chips. The peripheral-unit controllers may be configured somewhat differently depending upon whether the peripheral device utilizes data signals in parallel or in series. Data may be transferred directly between a computer memory unit and the peripheral devices without requiring the use of any computer working registers and without requiring subroutines to preserve an ongoing main program. Each peripheral-device controller can issue interrupt signals which are processed by the computer on a priority basis when they occur simultaneously. Some microengines employ two sets of programmed microcodes and each set is selectable by a switch, such as a wire jumper, for controlling either of two different kinds of devices.

The pin count of an integrated ISA-type bus controller and PCMCIA-type bus controller is reduced by utilizing a single external bus which supports both ISA-type and PCMCIA-type devices, and by placing control over the bus with the controller that controls the device that corresponds with the input address ADD.