A semiconductor integrated circuit which is reduced in size by having active and/or passive elements in an epitaxial layer having a [100] crystallographic surface, and having anisotropically etched regions with sloped [111] crystallographic surface walls which isolate adjacent semiconductor elements and/or regions of semiconductor material beneath said elements. Conductors interconnecting said elements are supported on the [100] and [111] crystallographic surfaces and contact said elements and/or said high conductivity regions through apertures in surface passivating protective coatings on said surfaces.
CROSS REFERENCE TO RELATED APPLICATIONS
This is a division of application Ser. No. 719,201, filed Aug. 30, 1976, which is a continuation of application Ser. No. 563,429, filed Mar. 31, 1975 abandoned; which is a continuation of application Ser. No. 401,319, filed Sept. 27, 1973, abandoned, which is a continuation of application Ser. No. 242,457, filed Apr. 10, 1972, (now abandoned).
A method of manufacturing a semiconductor device characterized in that after a fine groove has been formed in the surface of a semiconductor layer by dry etching, an insulating region is formed so as to fill up the fine groove.
A method of forming high quality inductors and capacitors in semiconductor integrated circuits utilizes one or more sealed air-gaps in a supporting substrate under the passive devices. The process is compatible with standard silicon processing and can be implemented with high temperature processing at the beginning, middle, or end of an integrated circuit fabrication process. A one micron air-gap in a high resistivity epitaxial layer results in a parasitic capacitance equivalent to 3.9 micron thick silicon oxide or a 11 micron thick depletion layer in silicon.
A semiconductor device comprises a V-groove isolation structure and an alignment mark having a sharp contour. The alignment mark consists of a locally thick portion of an oxide layer covering an epitaxial layer in which a V-groove is formed. The alignment mark is produced by a thermal oxidizing operation involved in the manufacturing procedure of the V-groove isolation structure.
A method of making an electrically-programmable memory array in which the memory elements are capacitor devices formed in anisotropically etched V-grooves, providing enhanced dielectric breakdown at the apex of the groove. After breakdown, a memory element exhibits a low resistance to a grounded substrate. The method includes forming access transistors in series with the memory elements, and polycrystalline silicon, deposited to form control gates of the access transistors, also forms address lines. Oxide is formed in the V-groove thinner than the gate oxide thickness formed for the access transistor, providing a lower programming voltage. These factors provide a very small, high speed device.
