In a data processing system for use in carrying out address translation of a preselected logical address so as to access a sequence of data elements stored in a memory (32) with an interval left between two adjacent ones of the data elements, a request control circuit (40) decides an element number in each cycle with reference to a logical distance (D) determined by the interval. The memory can be accessed in each cycle by a plurality of real addresses which are equal in number to the element number and which are calculated from the logical distance and the preselected logical address. Preferably, an address translation unit (80) is supplied with the preselected logical address and a part of the logical distance to produce a plurality of consecutive real page addresses (RPE and RPO) one of which corresponds to the preselected logical address. An address generator (50) produces a predetermined number of local logical addresses (EA.sub.0 .about.EA.sub.3) in response to the logical distance and the preselected logical address. The local logical addresses are combined with the consecutive real page addresses in an address combination circuit (100 ) to form local real addresses equal in number to the predetermined number. The local real addresses are restricted in number to the element number by a memory access controller (135) to be supplied to the memory as the real addresses.

A signal processing system (10) is described which has a processor (12), a random access memory (14) for storage of data, a read-only memory (16) for storage of both coefficients and instructions, and a selective cache memory (18) for storage of instructions that require high performance, and their associated buses. Instructions selected by the program are stored in the selective cache memory during their first call from the read only memory for use later in the program. An address sequencer (50) is described as one form of a control unit for executing the data stored in the selective cache memory. It generates a sequence of addresses repetitively, counts the number of iterations of the sequence of addresses, and informs the controller when a certain number of iterations have been completed. This creates a conditional branch statement in the program of the signal processing system (10).

A cache memory for use in a data processing system wherein data words identified by even address numbers are stored separately from data words associated with odd address numbers to enable the simultaneous transfer of two successively addressed data words to or from the cache memory by the transferring of a data word associated with an odd address number and a data word associated with an even address number.

A configuration for executing data processing processes has an operating system and various system resources that are accessed by the operating system using an access strategy for the execution of system processes. When there are different applications, different access strategies to the system resources are used. A method is also provided for determining the optimum access strategy to the system resources.

A data processing machine in which the cache operating cycle is divided into two subcycles dedicated to mutually exclusive operations. The first subcycle is dedicated to receiving a central processor memory read request, with its address. The second subcycle is dedicated to every other kind of cache operation, in particular either (a) receiving an address from a peripheral processor for checking the cache contents after a peripheral processor write to main memory, or (b) writing anything to the cache, including an invalid bit after a cache check match condition, or data after either a cache miss or a central processor write to main memory. The central processor can continue uninteruptedly to read the cache on successive central processor microinstruction cycles, regardless of the fact that the cache contents are being "simultaneously" checked, invalidated or updated after central processor writes. After a cache miss, although the central processor must be stopped to permit updating, it can resume operations a cycle earlier than is possible without the divided cache cycle.