A controller such as a programmable logic controller (PLC) is coupled to a load such as a contactor or motor starter through an interface that operates over a range of DC or AC voltage and couples a Start output of the controller to the load through a low current switch such as an opto-relay. The interface has a charging circuit coupled to the controller output, with a switching transistor, a load resistor and a capacitor in series. The low current switch is operated from accumulated charge in the capacitor and couples power to the load device. Charging of the capacitor to a threshold switches off of the transistor for an interval timed by a one-shot, during which the low current switch remains activated due to current draining from the capacitor. In an AC embodiment with a triac controller output, the capacitor continues to power the low current switch for the remainder of the positive AC half cycle, regardless of the triac, which may cease conduction due to lack of sufficient loading. The circuit substantially reduces the current dissipation of an interface between a PLC and a motor starter or contactor. The interface can include optically isolated signalling in both directions, including feed back of contact status and trip indications to inputs of the PLC.

The signals to be measured are transformed in the system to discrete time digital signals by synchronous sampling. These digital signals are then processed by a digital signal processor for vector detection and for computing digital feedback sent to the sampling gates. The analyzer has improved characteristics in the area of linearity, drift and test port signal injection because of its highly optimized architecture based on synchronous sampling with digital feedback. It possesses unique characteristics such as the ability to tune to a harmonic or a subharmonic of the excitation frequency and a good sensitivity in a high impedance environment.

A receive circuit for binary signals in time compression multiplexing systems mitigates effects of the local data decay tail and zero line wander by means of a sample-and-hold circuit, having a fast attack and a decay time constant equal to a combination of the transmission line, and dc blocking device time constants followed by a subtracting difference amplifier. Power feed of the line via dc blocking capacitors is thus possible. Also higher receiver gain is possible when sampling switch is left on during local data transmission without receiver instability.

A protection circuit for preventing momentary activation of the output of an output-isolated driver during power turn on. The protection circuit operates in a manner which prevents a buffer which is driven by the opto-isolator from turning on power transistors during power turn on, particularly in applications such as switching power supplies, motor controllers and the like.

A signal sampling circuit comprising a signal inverting amplifier with a gain greater than unity, an input clamp network including a feedback switch, and an output sampling network including a charge storage device and a sampling switch is disclosed. The amplifier input to which signals to be sampled are applied is clamped to the amplifier output potential via the feedback switch during non-sampling, clamping intervals. During subsequent sampling intervals, the feedback switch is disabled and the sampling switch is enabled to couple the amplifier output to the storage device, so that the storage device develops a voltage sample of amplifier output signals referenced to the clamping potential.