A dividing circuit comprises, connected in a ring, a plurality M of transistor stages, where M is an even integer. Each transistor stage comprises an input node, a clock node and an output node. A tri-state inverter stage has an input node connected to the output node of a preceding transistor stage in the ring, an enable node connected to the clock nodes of the transistor stages, and an output node connected to the input node of a subsequent transistor stage in the ring. Each transistor stage comprises a first pair of transistors of a first conductivity type connected in series between a first voltage level and an output node, and a second pair of transistors of a second conductivity type connected in series between a second voltage level and said output node, wherein control nodes of a first transistor of each said transistor pair are connected together to provide the input node for the stage, and control nodes of a second transistor of each said transistor pair are connected together to provide the clock node for the stage, whereby when an input clock signal is applied to the clock nodes of the transistor stages, an output signal is generated at the output node of the tri-state inverter in which each cycle represents M cycles of the input clock signal.

An output device is disclosed for restraining a ringing caused when the operation of a semiconductor integrated circuit device is speeded up. This output device includes first, second and third N channel transistors. The first N channel transistor has its gate electrode connected to receive an input signal, its drain electrode connected to an output terminal, and its source electrode connected to the drain electrodes of the second and third N channel transistors. The second N channel transistor has its gate electrode and drain electrode connected to each other and its source electrode grounded. The third N channel transistor has an on resistance value matching with the characteristic impedance of a load connected to the output terminal and has its source electrode grounded. When the level of the output signal is equal to or less than the threshold voltage of the second N channel transistor, the second N channel transistor is turned off, and the amount of an output current is limited by the on resistance of the third N channel transistor.

A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages. When a modulas control signal is low, the prescaler operates as five clocked inverters in series having an output which is fed back to the input of the initial stage. That is, the circuit operates as a five stage clocked ring oscillator wherein only one output changes on each clock edge. When a modulas control signal is high indicating that a divide by four is desired, the counter operates as a five stage ring oscillator for seven clock edges. On the eighth edge, feed forward circuitry forces the last three stages to change states simultaneously.

A programmable dividing circuit comprises a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages being configured so that when an output of the last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated which has one cycle for every N cycles of a clock signal applied to the transistor stages. The circuit includes a tri-state inverter selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages, wherein M is an even integer, and wherein the second plurality M of transistor stages includes at least some of said first plurality N of transistor stages, including said first stage, whereby when an output of a last stage in the divide-by-M sequence is supplied to the first stage, the circuit operates as a divide-by-M circuit in which an output signal is generated which has one cycle for every M cycles of a clock signal applied to the transistor stages. The circuit includes a switching circuit having at least two inputs and arranged to selectively connect to the first stage, the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence, whereby the circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.

A clock generator circuit for producing a clock signal while drawing reduced current drain is disclosed. The clock generator circuit includes a crystal oscillator which produces a periodic signal having a relatively small voltage swing, controlled by one or more reference voltages; the reference voltages are preferably produced by a sub-threshold biased voltage reference circuit. The small signal output of the crystal oscillator is applied to the first of a series of frequency divider stages, prior to amplification by a level shift circuit. Each divider stage includes a current switch which switches the current drawn through current divider legs to produce output signals to latches in the divider stage. Each divider stage also includes one or more current source switched latches, each controlled by current sources that are switched by the current switch. As a result, each divider stage divides the frequency of the oscillator output signal without requiring amplification of the signal, thus reducing the active current. The output of the last divider stage is applied to a level shift circuit to provide the large voltage swing clock signal.