There is provided a technology for preventing disabling of function of a clock monitoring circuit by a hacker in a microcomputer for IC card provided with a clock monitoring circuit as a countermeasure for a hacker. In the microcomputer for IC card provided with the clock monitoring circuit, the clock monitoring circuit is given the function to perform the detecting operation twice during one cycle, namely at the timings of rise and fall of the clock.

A device is proposed for monitoring the function of electronic equipment, in particular equipment controlled by microprocessors. In such devices, the regular occurrence of control pulses is monitored in that a capacitor which can be charged or discharged in accordance with the control pulses is connected to a threshold stage, which in the case of a persistent absence of control pulses generates a signal having a reset phase of predetermined duration and an active phase also of predetermined duration for the equipment in a periodic sequence. The durations, of the reset phase and the active phase are freely selectable independently of one another, the duration of the active phase preferably being substantially shorter than that of the reset phase.

Unique multi-level power amplifying circuitry is described that may be advantageously utilized in duplex portable radio transceivers which may be inserted into a vehicular adaptor for operation from the vehicle battery. Upon detecting the presence of the vehicular adaptor, the power amplifier may be operated at a second set of power levels which include levels greater than a first set of power levels for portable operation. The multi-level power amplifying circuitry of the present invention may be advantageously utilized in a variety of applications where duplex battery-operated radio transceivers may be inserted into a vehicular adaptor for operation from the vehicle battery.

To provide for starting of signal processing operations in a microprocessor (7), for example an automotive-type microprocessor, subject to frequent power interruptions, in which the processing operations are controlled by clock signals from a clock generator (1), and to insure that the microprocessor carries out its computation cycles only after the clock signal generator (1) provides clock signals at an adequate level appropriate for microprocessor operations, the level of the clock signals is sensed, for example in a peak rectifier (2, 3, 5) to reset the microprocessor when the clock signals have reached this level, thereby insuring commencing of processing cycles from a predetermined condition or state of the microprocessor at a time when adequate clock signals are available. The reset signal from the clock generator can be logically combined in a logic circuit (6) with externally generated reset signals, for example dependent on sufficient or suitable operating voltage being present for operation of the microprocessor from a power source (P), for example the battery of an automotive vehicle, to insure operation of the microprocessor only with adequate battery voltage being present, for example after termination of power drain by a starter motor.

A microcomputer executes a certain system program with a microprocessor according to a certain system clock. The microcomputer includes a watchdog timer circuit provided external to the microcomputer which counts a certain time interval by counting a certain timer clock which is separate from the system clock with a counter for a certain count and, upon completion of the counting, forcibly resets the microprocessor of the microcomputer. The system program of the microprocessor has a step of producing a reset output to the counter before a predetermined time only when the system action is normal. There is provided a timer circuit which counts the system clock of the microcomputer with a certain counter for a certain number of counts, counting a time interval which is slightly longer than the normal period of the timer clock of the watchdog timer circuit, and upon completion of the counting interrupts the microprocessor of the microcomputer. The system program of the microcomputer has a step in which reset output is supplied to the counter of the timer circuit in a repeated manner according to the monitoring result of the timer clock of the watchdog timer so as to respond to either the rise or the fall of the timer clock, and a step in which an abnormal output is produced to the outside in response to the interruption from the timer circuit. Thereby, the operation of the microcomputer and of the watchdog timer can be effectively checked and monitored.