Lookahead carry circuitry is provided for use with the consecutive bit stages of a digital adder whereby the computational throughput of an arithmetic logic unit can be increased (in other words reduced in time of operation). This is accomplished by reducing the number of gates required in the serial switching path to minimize the time delay for generation of carry output signals.
A high-speed carry increment adding device having a first module including a first adder, the first adder adding a desired number of first bit inputs and generating a plurality of partitioned sums and a partitioned carry as a result of the addition, and a second module including a second adder and a conditional incrementer, the second adder adding a desired number of second bit inputs regardless of the partitioned carry from the first adder and generating a plurality of partitioned sums and a partitioned carry as a result of the addition, the conditional incrementer inputting the partitioned carry from the first adder as an increment signal and incrementing the partitioned sums from the second adder in response to the inputted increment signal. Also, the second module includes a partitioned sum detector for detecting whether all of the partitioned sums from the second adder are "1" and generating a partitioned sum detect signal in accordance with the detected result. Also, the adding device includes at least one module arranged at a stage subsequent to and in parallel to the second module, the at least one module having the same construction as that of the second module, and an increment signal generator for generating the increment signal to the conditional incrementer of a desired one of the modules.
An arithmetic circuit for addition or subtraction includes a carry or borrow signal control section which includes a transfer gate having N-ch and P-ch transistors for transferring an input carry- or borrow-in as an output carry- or borrow-out. A signal transmission line is coupled to a source line or the earth during a sampling period and precharged during a precharge period, so that both a higher speed transmission of a carry or borrow signal and a reliable carry- or borrow-out signal can be obtained.
First and second input gates and an input inverter are provided for preprocessing respectively a plurality of input signals and an additional input signal, in addition to a carry gate and a sum gate. The first input gate is connected to each of a plurality of input bits for providing a logic low output only when all of its inputs are a logic high. The second input gate is connected to the plurality of input bits for providing a logic high only when all of its inputs are a logic low. The carry gate has three inputs and provides a carry-out logic high output when either (a) its first input from the first logic gate is a logic low; or (b) when both the second input from the second input gate and the third input from the inverter are a logic low. The sum gate has five inputs and provides a sum logic high output when either (a) both its first and second inputs from the output of a first input gate and from the inverter are logic low; or (b) its third input from the carry gate is at a logic low and either of the fourth or fifth inputs from the inverter or the second input gate are respectively a logic low.
An adder has first through third switching circuits, a logic circuit and an adding circuit part. The first switching circuit is coupled between a carry bit input terminal and a carry bit output terminal. The second switching circuit is coupled between a first power source voltage and the carry bit output terminal, and the third switching circuit is coupled between a second power source voltage and the carry bit output terminal. The logic circuit controls the ON/OFF states of the first through third switching circuits so that only one switching circuit is turned ON responsive to two binary values which are to be added in the adding circuit part. The propagation time of a carry bit signal from the carry bit input terminal to the carry bit output terminal is constant regardless of the number of bits of the adding circuit part.
A carry-look-ahead adder is provided which is implemented as a semiconductor integrated circuit. The integrated circuit includes a bipolar transistor coupled to the output terminal for providing an output indicative of the arithmetic operation. Impedance elements are coupled to the bipolar transistor and at least one FET is provided to control the on/off state of the bipolar transistor.
