A multiple user priority network is provided by a double section priority PROM. One section of the PROM is accessed by a current priority code stored in a priority register, and new request signals that appear on lines that are coupled to the requesting components to provide an address which contains a new access code. The second section of the PROM is accessed by the new access code, which is stored in a channel access code register, and the current priority code in the priority register to provide an address which contains a new priority code. The multiple user priority network of the present invention is thus capable of providing a updated priority for all of the requesting devices which is a function of the changes in the request status of the devices. The particular described implemented embodiment is a modified least-recently-used algorithm in which when more than one device is requesting access to a bus, the device which is currently in control will upon the initiation of the next cycle be assigned the lowest priority, and each of the other channels will have their priority increased by one.

A computer bus structure includes a plurality of separate bus segments on a mother board. Plugging in of each of a plurality of interface boards automatically connects the right-hand portion of a particular bus segment to the left-hand portion of an adjacent bus segment so that a local bus of the needed length is created from the separate bus segments by the plugging of a processor board and a plurality of interface boards into successive adjacent connector slots, respectively, of the mother board. Insertion of processor boards into a particular connection slot of the mother board prevents the two bus segments adjacent thereto from being connected.

A computer bus adapter device which is coupled to a true parallel computer bus is automatically set to a pre-determined configuration in response to configuration data provided to the bus by a host process. During a set-up portion of an initialization procedure, the adapter device recognizes a data sequence and uses information based on the recognized data sequence to configure itself to respond to its host process. In a specific embodiment, the desired configuration information is stored in non-volatile storage associated with the host process, such as a magnetic file or a non-volatile random access memory.

A dynamic random access memory ("DRAM") device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The DRAM device also includes a bank multiplexer for each bank of memory cells that selectively couples one of the internal address buses and one of the internal data buses to the respective bank of memory cells. Select signals generated by a command decoder cause the multiplexers to select alternate internal address and data buses responsive to each memory command received by the command decoder.

A dynamic random access memory ("DRAM") device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The DRAM device also includes a bank multiplexer for each bank of memory cells that selectively couples one of the internal address buses and one of the internal data buses to the respective bank of memory cells. Select signals generated by a command decoder cause the multiplexers to select alternate internal address and data buses responsive to each memory command received by the command decoder.