Logic output data of a plurality of channels simultaneously obtained from a circuit under test are sequentially input in a memory, and after inputting a predetermined amount of such data, they are compared with corresponding expected values. The input data are divided into blocks, each including a plurality of data. Whether a mismatch is present in the comparison results for each block is indicated by a respective block element, and such block elements are displayed in a predetermined arrangement. It is also possible to provide a conventional list display including the input timing corresponding to the comparison results in which a mismatch is present.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is related to U.S. application Ser. No. 737,467.
BACKGROUND OF THE INVENTION
The present invention relates to a logic analyzer which is employed for analyzing the state of operation of a logic circuit in an apparatus which is operated, for example, by a microprocessor.
Heretofore, there has been proposed, for example, in U.S. Pat. Nos. 4,425,643 and 4,434,488, a logic analyzer of the type that sequentially inputs into a memory waveform output data simultaneously obtained from respective parts of a logic circuit and decides from the input data whether the logic circuit is normally operating or not.
In this kind of logic analyzer, predicted values, i.e. expected values, or output data obtained from a normally operating circuit are prestored as the expected values, and data obtained from a circuit under test is compared with the expected value for each state and when their mismatch is detected, it is decided that the circuit under test is defective.
For deciding only whether the circuit under test is non-defective or defective, it is necessary only to decide it as defective when one defective point is detected. In order to facilitate repair of the defective circuit, however, it is necessary to locate the malfunctioning portion. To meet this requirement, it is customary that data obtained from the circuit under test are displayed directly as logic values and that when a mismatch with the expected value is detected, a bright spot L is generated at the mismatched data position, indicating the occurrence of malfunction, as shown in FIG. 1. This method of display is called a list method. In this list, a numeric value field SEQ in the left-most column shows the timing numbers indicating the order of generation of output patterns, and the logic values in the respective columns at the right-hand side thereof show the data obtained from the circuit under test. GR0 and GR1 each show data of respective bits of eight channels, and GR2 data of respective bits of 16 channels. Each of GR3 and GR4 shows, in hexadecimal representation, four numbers each representing data of four binary bits corresponding to four channels. For example, A6A6 indicates 1010, 0110, 1010 and 0110, thus representing data of 16 channels in total.
In the case of adopting the list method, the list shown in FIG. 1 is a small part of the entire list, and in order to examine the comparison results of all patterns, the operator must observe the entire list while scrolling pages in the order of generation of the patterns. The number of patterns required for testing one circuit is about in the range of 1000 to 40000, though it differs with the scale of the circuit. Therefore, it is very laborious to effect eye inspection of 1000 to 40000 comparison results according to the list method.
Incidentally, there are cases where the circuit under test includes a part which operates at a relatively high frequency, that is, at a high speed, and a part which operates at a low speed. When high-speed and low-speed logic outputs are simultaneously obtained to be displayed, they must be input at a speed which permits correct observation of the high-speed output, and the inputting of the low-speed logic output at that speed results in unnecessarily much data being input. To avoid this, it is the general practice in the prior art to input the high-speed and low-speed logic outputs in different memories at speeds corresponding to their logic operation speeds, to read out the memories in accordance with the input speeds and to display the high-speed and low-speed logic outputs on the display screen of a display using the same time axis.
Conventionally, in such a case, the high-speed and low-speed logic outputs are sequentially arranged on the display screen in the order of output channels CH0 to CH7 of the circuit under test irrespective of the logic speeds of the input data, as shown in FIG. 2. A time axis LM is displayed at the lowermost position on the display screen. With this method of display, however, it cannot readily be known which waveform is the waveform of the high-speed or low-speed logic output. Accordingly, the operator must observe the individual displayed waveforms while judging from the signal input set state or the like whether the waveform is the high-speed or low-speed logic output for each channel. This is very inefficient.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a logic analyzer which allows ease in locating a malfunctioning part of a circuit under test.
Another object of the present invention is to provide a logic analyzer which displays high-speed logic output waveforms and low-speed logic output waveforms in distinction from each other.
According to the present invention, data obtained from a circuit under test and the corresponding expected value are compared, and a plurality of such comparison results are displayed using one representative decision-indicator block element which differs depending upon whether a mismatch is present in the comparison results or not. Such representative decision-indicator block elements (hereinafter referred to simply as block elements) are displayed in an array, thereby displaying a large number of comparison results on one screen. By providing a display of the conventional list method in connection with the block element indicating the presence of a mismatch, the malfunctioning part can easily be located.
Further, according to the present invention, high-rate and low-rate logic outputs are input into different memories from the circuit under test at speeds suitable to them. The memories are read out in accordance with the high and low logic operation speeds, respectively, and displayed on the display screen of the same display using the same time axis. In this instance, the high-rate logic output waveform and the low-rate logic output waveform are displayed separately and a display is produced to indicate the position where they are separated.
Priority Data
May 28, 1984 [JP] 59-108921 May 30, 1984 [JP] 59-110380
A memory testing device having n test channels for simultaneously testing n memories. A pattern generator generates a sequence of test patterns each including a write enable signal, expected value data, write data and an address signal. In each test channel, the write enable signal WE is repeatedly applied via the AND gate to a terminal WE of the corresponding memory under test to write the data thereinto at an address designated by the address signal. Data read out therefrom is compared to the expected value data to produce a comparison result. The comparison result is used to control the AND gate so that when the comparison result indicates coincidence between the compared data, the write enable signal WE is inhibited.
In a method and apparatus for displaying data on a video display that is controlled by a video controller, the video controller is coupled to a high-speed memory and a low-speed memory. The memories have separate data paths. A video address corresponding to a location on the video display is received. If a specified address bit is in a first state, then data is displayed from the high-speed memory. If the specified address bit is in a second state, then data is displayed from the low-speed memory. The specified address bit may be a high order address bit that is not utilized by a conventional VGA controller to transmit address information.
A diagnostic system for a digital signal processor, having an input module, an output module and a plurality of successive processing modules defining a signal processing path, monitors various internal test points within each module. Any one of the test points may be connected to a diagnostic bus. The output of the diagnostic bus may be appropriately modified and input to the output module in lieu of the digital signal from the last processing module to provide a diagnostic display.
A semiconductor test system comprises an expected value storage area for storing expected values of output data supplied from a semiconductor device under test, a memory device for storing output data directly supplied from the semiconductor device under test in the form of the identical code with that of the expected value storage area, and a comparator for comparing output data from the memory device directly with expected values from the expected value storage area without any conversion.
An automatic testing instrument determines the operational status of an equipment under test on a real time basis by first generating from a stimulus memory a pattern for stimulating the equipment which, when stimulated by the pattern, sends out a response pattern, which is transmitted back to the automatic testing instrument. The testing instrument then takes the received response pattern and compares it with a pre-determined pattern stored in a comparator. If the response pattern differs from the expected pattern, an error signal is sent to indicate to the user of the testing instrument that the equipment under test is operating erroneously, for that particular pattern.
