A method and apparatus for separating sync pulses by charging a capacitor to the sync tip voltage level during occurrence of a sync pulse and discharging the capacitor to the back porch voltage level for an equal duration. The discharge duration is determined by decrementing an up/down counter that was incremented during the sync pulse. A comparator separates the sync pulses by comparing the composite video signal with the voltage on the capacitor.

A digital data slicer circuit causes the slicing level to track a teletext signal in optimum fashion even if the teletext signal has many successive zero crossings. The digital data slicer circuit substantially prevents any lock-in in either of two other, stable states. This is achieved essentially by applying a zero signal via two changeover switches to an accumulator and a sign inverter when many successive zero crossings are detected by a logic circuit that controls the changeover switches.

A detector for vertical synchronizing pulses comprises a nonwrapping up/down counter and a comparator. The counter level samples a composite synchronizing signal at a sampling rate. The counter has a numerical output which increases responsive to detection of said level during a sample interval and decreases responsive to nondetection of said level during a sample interval. The comparator generates a vertical sync detection pulse when the numerical output of the counter is greater than a reference value. In order to provide hysteresis, the numerical value os alternately one of first and second numerical reference counts, the first reference count being greater than the second reference count. The comparator initiates the vertical sync detection pulse when the numerical output of the counter rises above the first reference count and terminates the vertical sync detection pulse when the numerical output of the counter falls falls below the second reference count. The numerical reference supplied to the comparator is changed at times corresponding to initiation and termination of each vertical sync detection pulse. A pulse shaping circuit may comprise a latch for sampling the output of the comparator and generating a vertical synchronizing signal.

A signal detector circuit arrangement for detecting synchronizing pulses contained in a digital television signal by the use of a separating stage wherein, during the time intervals in which television signal portions are separated in the separating stage and at the same time an instantaneous sampling value exceeds a stored sampling value in the direction of the level of the synchronizing pulses, the stored sampling value is replaced by the instantaneous sampling value and simultaneously a marker pulse is generated. In each time interval between consecutive synchronizing pulses, the stored sampling value is erased at a presettable instant which is identical for all the time intervals. The final marker pulse of such an erasing procedure marks a detected synchronizing pulse.

A method and apparatus for defeating copy protection signals in a video signal, and also for providing copy protection signals for a video signal, is disclosed. The defeat technique generally utilizes a particular pulse position shifting, modulation, etc., of AGC, normal sync and/or pseudo sync pulses to increase the separation between the pulses. Various embodiments are disclosed including selective shifting of the relative positions of either the sync/pseudo sync or AGC pulses, trimming portions of the sync/pseudo sync and/or the AGC pulses and narrowing of either the sync/pseudo sync and/or the AGC pulses, all to provide the selective position separation between the sync/pseudo sync and AGC pulses. The copy protection technique includes various embodiments for dynamically varying the sync/pseudo sync and AGC pulse separation by applying a modulation of the above position shifting, trimming and/or narrowing techniques over selected time periods to cycle from the copy protection condition to the copy protection defeat condition, back to the copy protection condition.