An electrically reconfigurable multi-chip module (MCERD) comprises three electrically reconfigurable integrated circuits (ERICs) enclosed in a package. The package provides for more "extra-package" connections between the ERICs and package pins than it does "intra-package" inter-chip connections. However, configuration connections between ERICs are intra-package. The MCERD is mounted on a daughterboard which provides connections between package pins and between package pins and pins of the daughterboard. The connections between package pins define "extra-package inter-chip" connections that typically far exceed the number of intra-package inter-chip connections. The connections between package pins and daughterboard pins connect the MCERD to a host system when the daughterboard is mounted on the host system motherboard. When the MCERD and daughterboard are installed in a host system, the MCERD can be electrically configured and then operated as configured. A feature of this MCERD is that a system developer can configure the inter-chip connections by appropriate design of the daughterboard.

A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second and third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.

A master slice type integrated circuit for providing various circuits by altering the routing of interconnections comprises a plurality of input/output cells arranged in a peripheral region on a semiconductor chip, the input/output cells each comprising pads for connection with an external circuit, input wiring regions each for accommodating input interconnecting lines transmitting input signals applied to the pads, and output circuit regions each for forming output buffers; and a plurality of basic cells being arranged in a region on the chip surrounded by the arrangement of the input/output cells. Two adjacent input/output cells are paired with each other. The output circuit regions of the pair of the input/output cells are arranged in the vicinity of a boundary of the pair. The input wiring regions of the pair are arranged in the vicinity of boundaries with respect to other pairs.

A standard logic block, or macrocell, is provided for use on programmable logic devices. The macrocell uses RAM to perform logic functions, and further includes circuitry which allows writing of data to the RAM during use. Each logic block can be configured at programming time to be either a user RAM, allowing the user to write data to such memory during use, or configured as performing logic functions. The contents of macrocells configured as providing logic functions cannot be charged except by reprogramming the device.

A programmable logic device of a single semiconductor chip includes a plurality of programmable AND-OR logic blocks, each block including an AND gate array and an OR gate array and at least a pair of input and output lines; a plurality of input/output buffer blocks, each block including at least one input and output lines; and a plurality of interconnection lines across which the input and output lines extend. A programmable switch is provided at each of the intersections between the input and output lines and the interconnection lines, so that each of the input and output lines are selectively connected to a desired one of the interconnection lines. Preferably, each of the interconnection lines further includes at least one programmable switch so that each of the interconnection lines may be divided into a desired number of segments which are electrically isolated from one another. A programmable logic device may include a plurality of programmable logic unit cells and first interconnecting means for interconnecting the cells, each of the cells including a plurality of programmable AND-OR logic blocks, a plurality of input/output blocks and second interconnecting means for interconnecting the blocks.