A structure and process for forming a contact to a semiconductor substrate on a semiconductor device comprises the step of forming a patterned mask over a semiconductor substrate and over a field oxide region, then etching the semiconductor substrate and the field oxide region to form a trench. The trench comprises a bottom and a first sidewall consisting of silicon and a second sidewall comprising field oxide. The etching step removes a part of a doped region in the substrate. Next, a blanket nitride layer and a blanket oxide layer is formed over the substrate, and a spacer etch is performed on the nitride and oxide layer leaving nitride and oxide over the first and second sidewalls. The trench bottom is oxidized to form a layer of oxide over the bottom of the trench thereby insulating the trench bottom, and the oxide encroaches under the nitride and oxide on the sidewalls to join with the field oxide. The nitride and oxide is removed from the sidewalls, and a conductive layer is formed over the exposed trench sidewalls, the trench bottom being insulated from the conductive layer by the oxide layer over the bottom of the trench. The oxide on the bottom of the trench contacts the field oxide. The contact is isolated from the substrate along the trench bottom and the second sidewall, making contact with the substrate only in the area of the first sidewall.

In a cell capacitor of a dynamic random access memory cell according to the present invention, an insulation film is formed on the surface of a fine trench formed in a silicon semiconductor substrate. A contact hole is formed in the insulation film in a region on the side wall of the trench. A polysilicon film is formed on the side wall of the trench in a hollow-cylindrical shape. A silicon layer is epitaxially and selectively grown on the polysilicon film and on the silicon substrate exposed through the contact hole. The polysilicon film and the silicon layer constitute an information storage electrode. At least the silicon layer of the information storage electrode is electrically connected to a source or a drain region of a transfer transistor of the memory cell. A gate insulation film is formed on the surface of the silicon layer. A counter electrode is formed such that the counter electrode is embedded in the trench.

A semiconductor memory configuration in a semiconductor substrate includes bit lines, word lines, and memory cells each including one memory capacitor and one MOS selection transistor having two conducting regions and a gate electrode. Each memory capacitor is connected to one of the conducting regions of the transistor. The other of the conducting regions of the transistor is connected to one of the bit lines, and the gate electrode of the transistor is connected to one of the word lines. An insulating field oxide or buried insulating oxide with substantially vertical sidewalls is provided. A trench lies adjacent to the insulating field oxide or buried insulating oxide and adjacent to one of the conducting regions. The capacitors are each disposed in one trench for each memory cell. A first insulating layer covers the inner trench wall surface. A first electrode of the capacitor is disposed perpendicular to the substrate surface on the first insulating layer completely inside the trench. A second insulating layer is disposed on the first electrode. A second electrode is disposed vertically on the second insulating layer in the trench. A contact is connected between the first electrode of the capacitor and one of the conducting regions of the transistor laterally through an opening formed in the first insulating layer on the inner trench wall surface. Methods for producing the semiconductor memory configuration and a memory matrix having at least four of the memory cells, are also provided.

A large scale integrable memory cell including a field effect transistor lying at a bit line and further including a storage capacitor which is formed by the wall of a trench and a cooperating electrode. The active region of the storage cell which lies outside the trench is fashioned in the form of a strip. The end face forms one part of the trench edge and the remaining portion of the trench edge is surrounded by a field oxide region.

A semiconductor memory has a first insulating layer formed on one major surface of a silicon single crystal substrate having a hole portion. The hole portion is filled with a material of a first conductivity type up to the depth of the first insulating layer. A first single crystal silicon layer is formed on the first insulating layer and a diffused region of the first single crystal silicon layer is formed on the first insulating layer and on the material of a first conductivity type. Source and drain regions are formed by doping the first single crystal silicon layer with a first impurity up to high degree of concentration. A second insulating layer is then formed on the first single crystal silicon layer with a low resistive portion formed on this second insulating layer to form source and drain regions. A second single crystal silicon layer is formed along the wall surfaces of the second insulating layer and the low resistive portion. A gate insulating film is formed along wall surfaces of the second single crystal silicon layer and the diffused region on the low resistive portion and having the hole portion on the material of a first conductivity type. Finally, a gate electrode is formed by filling the hole portion of the gate insulating film with the material of a first conductivity type.