A channel apparatus including a transfer controller responsive to an input data transfer command, for translating virtual block address data designated by a channel command word (CCW) into RBA data to store the translated RBA data. The CCW commands the DMA transfer of the data over a plurality of subsequent blocks of the external memory. The translated RBA data are written in a real address storage section in a write mode. The controller outputs a transfer start instruction to a DMA transfer section after outputting an initial value of a DMA address to a DMA transfer section and writing a predetermined amount of the RBA data to the storage section. The DMA transfer section performs the DMA transfer of the data to the external memory in a read mode in accordance with the transfer start instruction while the data is being input from the external device. The transfer section generates a memory request every time performing the DMA transfer of one word of the data. At the same time, the transfer section outputs the DMA address to the storage section. In the storage section, a real address is produced in combination with the offset data in the DMA address and the stored RBA data at the read storage address in the DMA address to output the produced address to the external memory in response to the memory request.
A fuzzy data record pointer is utilized for identification of both a target file and a target data record within the target file. A target data record is accessed from a target file, selected from a set of N related files, utilizing a fuzzy data record pointer ("fuzzy", as used herein, means that the data record pointer need not be coincident with the actual data record address). A modulus for the data record pointer divided by N is computed. This modulus is used to select the target file. A data record address is computed for the target data record utilizing the data record pointer and modulus. In this manner a fuzzy data record pointer is utilized to determine both the target file from a set of N related files and the target data record to be accessed within the target file.
An apparatus and method for performing direct memory access (DMA) to input/output (I/O) devices are described. In order to overcome storage limitations of a DMA controller, channel control blocks (CCBs) are stored in external memory. The DMA controller is programmed to reference a particular address of the external memory when a predetermined bit, referred to as a chain bit, in a current channel control block is set. The DMA controller will then perform a memory read operation on that area of memory and store a retrieved channel control block at a location previously utilized by an earlier channel control block. This process will continue until the chain bit is reset, at which time a DMA operation is complete. Dynamic chaining is easily accommodated whereby channel control blocks can be dynamically changed during the DMA access to provide a flexible I/O system. The apparatus and method may be used to implement dynamic chaining without incurring race conditions. A wait bit is provided in each channel control block and, when this bit is set, the DMA controller will suspend operations thereby providing an opportunity for updating a chain of CCBs without incurring errors due to race conditions. Once the chain has been modified, the wait bit is reset and processing safely continues.
The present invention is an apparatus and method for selecting one of a first and a second storage element in response to a control signal issued by a processor in a low pin count device. The apparatus comprises a decoder to receive the control signal and an address signal having a select bit indicative of one of the first and the second storage elements. The decoder generates a select signal to access one of the first and the second storage elements based on the select bit.
A DMA transfer device according to the present invention allows data to be transferred from non-consecutive addresses. A logical address controller checks if logical addresses of data transferred from an input/output bus are consecutive. If they are not consecutive, the logical address controller sends an address non-consecutive interrupt to an input/output controller. The input/output controller sets a physical address, corresponding to the logical address received from the input/output bus, into a physical address controller. The physical address controller checks if a page change has occurred in the physical address and, if it detects the page change, sends a page change interrupt to the input/output controller.
A hardware accelerated I/O data processing engine to execute a minimum number of types of I/O data processing commands in response to a stimulus from a host computer. The data processing engine, referred to as a command interpreter includes a command queue, a logic unit, a multiple purpose interface, at least one memory, and a controlling state machine, that each operate in concert with each other and without software control. The types of commands executed by the command interpreter can include, but are not limited to, an Initialize, Copy, DMA Read, DMA Write, Cumulative Exclusive OR, Verify, Compare, and ECC Check. The execution of commands that specify a source data location and a destination data location are characterized by a plurality of reads to an internal cache from the source data location for each bulk write from the internal cache to the destination data location. The locations of the data operated on by the command interpreter include a local I/O controller memory and a non-local I/O controller memory accessible to the command interpreter by way of an I/O bus.
