A semiconductor device and a method of making the same capable of simplifying the process of making and reducing the cost of making. In the method a first layer is formed which has a plurality of conductors at its edge portion. Thereafter, a second layer is formed on the first layer which is to be selectively etched to form a pattern. During the etching, current is detected from the conductors and the etching is stopped dependent on the current detected from the conductors. The semiconductor device includes a transparent electrode on a substrate the transparent electrode having protrusions which have a top surface. A first insulation layer exists between the protrusions. There is a color emitting layer on the top surfaces of the protrusions and the insulation layer. The method includes the steps of: forming a first layer which has a plurality of conductors at its edge portion; forming a second layer to be selectively etched on the first layer including the conductors, to form a pattern; selectively etching the second layer and detecting a current a generated from the conductors during the etching; and stopping the etching in accordance with the current detected from the conductors.

A test structure for submicrometer metrology as used in integral circuit manufacture comprises a bridge conductor divided into three segments by pairs of voltage taps. A first segment has no intermediate taps; a second segment has a number of dummy taps intermediate its ends; and a third segment has a single central tap, which may typically be formed in a different step than the remainder of the test structure, intermediate its ends. Preferably, the central tap extends from the same side of the bridge conductor as the taps at the ends of the third segment thereof. In order to evaluate a manufacturing operation, for example, to monitor the accuracy of registration of successive manufacturing steps, test signals are applied successively between the pairs of pads. Comparison of the response of the first and second segments to the test signals allows evaluation of the segment-shortening effect of the taps; comparison of the response of the two portions of the third segment to the test signals allows evaluation of their lengths, and thus of the offset, that is, the accuracy of registration of the step used to form the central tap. A plurality of substantially identical test structures are formed, for example, on an integrated circuit substrate. Offsets measured with respect to each of the substrates are summed using a least-squares technique, to allow separation of tool-wide misalignment errors and errors in the generation of a particular pattern or similar tool used to form a test structure. By summing the offsets measured with respect to a large number of test structures, random errors due to the presence of dust or other contaminants on the tools are effectively eliminated.

A test structure for submicrometer metrology as used in integrated circuit manufacture comprises a bridge conductor divided into three segments by pairs of voltage taps. A first segment has no intermediate taps; a second segment has a number of dummy taps intermediate its ends; and a third segment has a single central tap, which may typically be formed in a different step than the remainder of the test structure, intermediate its ends. Preferably, the central tap extends from the same side of the bridge conductor as the taps at the ends of the third segment thereof. In order to evaluate a manufacturing operation, for example, to monitor the accuracy of registration of successive manufacturing steps, test signals are applied successively between the pairs of pads. Comparison of the response of the first and second segments to the test signals allows evaluation of the segment shortening effect of the taps; comparison of the response of the two portions of the third segment to the test signals allows evaluation of their lengths, and thus of the accuracy of registration of the step used to form the central tap.

A method and apparatus for measuring sheet resistivity of a layer manufactured under the influence of a plasma, wherein a current is generated using two voltage or current sources in a circuit that is composed of a first current branch, a sheet resistivity, and a second current branch. The current includes the parasitic current I.sub.P injected into the layer by the plasma, this having a first and second part which are symmetrically supplied into the two current branches which respectively have an identical resistance overall. The currents I.sub.A and I.sub.B thus actually flowing in the first and second current branch are respectively directly measured, or measured on the basis of the voltage drop-off at known precision resistors. A measured current I.sub.M which is independent of the plasma influence is calculated therefrom by averaging, and the sheet resistivity is calculated from I.sub.M and by measuring the voltage drop-off at the sheet resistivity.

Imaging instruments for inspecting products, such as semiconductor chips, are calibrated by providing a reference test structure having features which can be located by electrical measurements not subject to tool-induced shift and wafer-induced shift experienced by the imaging instrument. The reference test structure is first qualified using electrical measurements, and is then used to calibrate the imaging instrument. The electrical measurements may be made by forcing a current between a plurality of spaced reference features and an underlying conductor, or may be made by capacitive, conductive, magnetic, or impedance-measuring techniques. Capacitive techniques may also be used to detect features not susceptible of resistance measurement, such as dielectric or insulative materials, or metallic structures not accessible for forcing a current therethrough. A series of test structure elements may be fabricated with one component of each being spaced at progressively greater distances from an arbitrary baseline, such that a null-overlay element may be identified.