An integrated circuit structure with a first layer that has a first conductive area and a second conductive area that is electrically isolated from the first area, and a second layer that has a third conductive area and a fourth conductive area that is electrically isolated from the third area. An edge of the first conductive area has an extended region that protrudes into the second conductive area. An edge of the fourth conductive area has an extended region that protrudes into the third conductive area. The first area is electrically coupled to the fourth area, and the second area is electrically coupled to the third area.

A first mask includes a plurality of vertical portions and a plurality of horizontal portions. The vertical portions and the horizontal portion are crossed, thereby forming a plurality of closed areas. A second mask is placed over the first mask that exposes the closed areas for forming sources and drains. A third mask formed over the closed areas to expose a portion of the closed areas for forming contact holes, and a fourth mask includes a first portion and a second separated portion, the first portion and the separated second portion cover the first contact holes.

A semiconductor memory device includes a plurality of active regions, and a gate electrode in a fish bone shape arranged on each active region. In each active region, a plurality of source regions and a plurality of drain regions are arranged in a matrix manner. The source regions are commonly connected to a source line, and the drain regions are each connected to a lower electrode of a different memory element. According to the present invention, it is possible to assign three cell transistors connected in parallel to one memory element, so that an effective gate width is further increased.

A cellular transistor structure is disclosed which incorporates a polysilicon gate mesh. In one embodiment, the silicon under the polysilicon is of an N-type while the exposed area not covered by the polysilicon is doped with a P dopant to form P-type source and drain regions. Metal strips are used to contact the rows of source and drain cells. By forming the openings in the polysilicon mesh to be in a diamond shape (i.e., having a long diagonal and a short diagonal), the source and drain metal strips, arranged in the direction of the short diagonals, can be made wider and shorter, thus reducing the on-resistance of the transistor without increasing the area of the transistor.

On a semiconductor substrate are formed a plurality of pedestal regions which are of the same conductivity type as the semiconductor substrate. Insulating layers are formed on side surfaces of the pedestal regions. On the insulating layers are formed gate electrodes which are connected together. First and second regions are formed within top portions of the pedestal regions and the semiconductor substrate. The first and second regions serve as source/drain regions and are of the opposite conductivity type to the semiconductor substrate. The first regions, the second regions and the gate electrodes function to form a single transistor because the gate electrodes are connected together.