A toroidally-connected distributed-memory parallel computer having rows of processors, with each processor having an independent memory. The computer includes at least one common I/O channel adapted to be connected to a single row of processors by buffering mechanisms. Each buffering mechanism is associated with one processor of the single row of processors.
An apparatus for multi-dimensional computation which comprises a computation engine, including a plurality of processing modules. The processing modules are configured in parallel and compute respective contributions to a computed multi-dimensional image of respective two dimensional data sets. A high-speed, parallel access storage system is provided which stores the multi-dimensional data sets, and a switching circuit routes the data among the processing modules in the computation engine and the storage system. A data acquisition port receives the two dimensional data sets representing projections through an image, for reconstruction algorithms such as encountered in computerized tomography. The processing modules include a programmable local host, by which they may be configured to execute a plurality of different types of multi-dimensional algorithms. The processing modules thus include an image manipulation processor, which includes a source cache, a target cache, a coefficient table, and control software for executing image transformation routines using data in the source cache and the coefficient table and loading resulting data in the target cache. The local host processor operates to load the source cache with a two dimensional data set, loads the coefficient table, and transfers resulting data out of the target cache to the storage system, or to another destination.
A system of elementary processors in array form organized in accordance with a plurality of nodes with SIMD operation, each having a plurality of elementary processors connected to one another so as to form a ring of elementary processors, each elementary processor being associated with a connection cell connected to the cells of neighbouring elementary processors in order to form a ring network. Each SIMD node is provided with a memory and addressing module ensuring an addressing independence of the node, as well as a control unit connected to the control units of neighbouring nodes in order to form an internode control network in which priority tokens circulate, each memory and addressing module of a node being connected to the memory and addressing module of neighbouring nodes so as to form an internode data network. The system may find one application in the simulation of fluid flows.
A parallel data processing system uses a parallel learning method capable of having sufficient parallelness to shorten learning time and has plural data processing units, each connected to a data transfer unit and having a unit for holding execution parameters as are required for data processing, a unit for holding partial sample data which comprises at least part of the full sample data necessary for the required data processing, an adjustment value calculation unit which calculates, from partial sample data stored in the unit for holding partial sample data and from the execution parameters held in the execution parameter holding unit, adjustment amounts related to the execution parameters with regard to the partial sample data and, further, an accumulator which, when calculating the overall total of the execution parameter adjustment amounts with regard to the full sample data, accumulates the adjustment amounts related to the execution parameters with regard to the partial sample data at the data processing units and the adjustment amounts related to the execution parameters with regard to the partial sample data at other data processing units by the data transfer unit.
A parallel computer of this invention includes a plurality of memory elements and a plurality of processing elements and each of the processing elements is connected to logically adjacent memory elements. For example, the processing elements which corresponds to a logical position (i, j) is connected to the memory elements which correspond to a plurality of logical positions (i, j), (i, j+1), (i+1, j) and (i+1, j+1). It is preferable if each of the memory elements can be accessed from the exterior. According to this invention, efficient memory access can be made and the parallel processing can be performed at high speed without increasing the hardware amount and making the control operation complicated. Further, the operation speed of the image processing can be enhanced by constructing an image memory by use of a plurality of memory elements and causing the processing element to effect the image processing in a distributed and cooperative manner.
A multinodal system is one-way interconnected, two-way interconnected or, more generally, (n)-way interconnected, where (n) is an integer. In a one-way interconnected system, only one connection element couples any two nodes. Or, put another way, only one communication path exists between every node and every other node. A two-way interconnected system, on the other hand, has two connection elements coupling each pair of nodes. Likewise, an (n)-way interconnected system provides (n) independent connection paths between each pair. Such systems are characteristic in that the relationship between the number of independent buses (b), the number of nodes (v), the number of ports (r), and the degree of interconnectedness (n) can be expressed by the equation ##EQU1## Two-way and (n)-way interconnect arrays may be adapted for use in fault-tolerant communications.