An arrangement for communication between two CPUs which allows diagnosis of whether the cause of an interrupt in communication between the CPUs is due to a routine interrupt or a failure in the communication line. Timers generate overflow signals in the event that data from one or the other CPU is late in arriving. Lateness is determined by comparing the timer values to stored values in memory. Control units respond to the timers and switch the transmission level of the CPUs so that they pass a predetermined signal pattern between themselves, indicating that the interrupt is in effect but that communication lines are still open. When one of the CPUs fails to detect the confirmation signal, the CPU causes a communication failure to be indicated.
A system for communicating data between two control units each capable of executing independent operations and having a memory for operations, the system is provided with a new data generator on one control unit. The new data generator generates new data for a selected item of the other control unit. The new data is combined with address data corresponding to the selected item of the memory of the other control unit to generate transmission data. The transmission data is sent to the other control unit and the new item data is written on the memory at the address specified by the transmission data. The data communication system communicates between the two control units data for a first kind of operations and data for a second kind of operations selectively. The first kind data is communicated repeatedly while the second kind data is communicated a single time.
Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented. Specific support falls into three areas: the extension of snooping to support multiple caches, the support of shared data between the two processors, and the provision of a processor and upgrade arbitration protocol that permits dual processors to share a single grant signal line.
A method and apparatus for operating a peripheral system having one or more peripheral devices coupled to at least one bus is described. When a bus master initiates a transaction with a peripheral device that ends in an abort condition (such as a Master Abort condition in a PCI architecture), the bus master generates an interrupt (such as the System Management Interrupt) to a central processing unit (CPU). When the interrupt is received, the CPU then attempts to determine the cause of the abort condition. For example, if the peripheral device is operating in a low power consumption mode, the CPU attempts to power up the device so that a retry of the transaction will be successful. Since the peripheral devices can be kept in a low power consumption mode until accessed by a bus master, the power consumption for the computer system is greatly reduced.
