A computer bus includes a first original signal line, a second redundant signal line, circuitry connected to the first original signal line and the second redundant signal line for driving the first original signal line and the second redundant signal line so as to convey on each identical information, circuitry for receiving signals on the first original signal line and the second redundant signal line, and error checking circuitry for comparing the signals on the first original signal line and the second redundant signal line and for indicating an error if the signals differ. By providing redundant signals for each signal that cannot be check with parity (for example wired-OR signals), the potential for single undetected points of failure is eliminated. In accordance with another embodiment of the invention, a computer having multiple modules connected by a backplane bus.

An information processing system has a plurality of processor circuits, each of the processor circuits including internal circuits and an internal processing result outputting circuit, the system having an internal data selection circuit connected to each of the processor circuits and at least one fault detection circuit. The internal processing result outputting circuit of each of the processor circuits outputs respective result data processed by respective ones of the internal circuits in the processor circuit. Each of the internal data selection circuit selects and outputs one selected result data output from the internal processing result outputting circuit of each of the processor circuits, at a predetermined timing. The fault detection circuit outputs a result of a comparison among the data selected by the respective internal data selection circuits of the processor circuits or among the data output at each predetermined timing by the processor circuits.

An apparatus, and a corresponding method, are used for seeding differences in lock stepped processors, the apparatus implemented on two or more processors operating in a lock step mode. Each of the two or more processors comprise a processor-specific resource operable to seed the differences, a processor logic to execute a code sequence, in which an identical code sequence is executed by the processor logic of each of the two or more processors, and an output to provide a result of execution of the code sequence. The processor outputs, based on execution of the code sequence is provided to a lock step logic operable to read and compare the output of each of the two or more processors.

An apparatus, and a corresponding method, are used for seeding differences in lock stepped processors, the apparatus implemented on two or more processors operating in a lock step mode, wherein each of the two or more processors comprise a processor-specific resource operable to seed the differences, a processor logic to execute a code sequence, wherein an identical code sequence is executed by the processor logic of each of the two or more processors, and an output to provide a result of execution of the code sequence. The processor outputs, based on execution of the code sequence is provided to a lock step logic operable to read and compare the output of each of the two or more processors.

A communication device includes a storage medium for storing a program and information used to detect any error in the program, to prevent the communication device from further abnormal operation when an error occurs in the stored program. The occurrence of an error in the program is detected by performing a calculation based on the stored program, and comparing the result of the calculation with the above-described information stored in the storage medium. A predetermined operation is further performed depending on the result of the comparison.