The invention relates to UPC/NPC method for guaranteeing the quality of service in an asynchronous transfer mode networks. The method comprises a first step of performing the operation of UPC/NPC for a stream of CLP=0 cells, based on PCRA algorithm (Po) for the conventional stream of CLP=0 cells. And, UPC/NPC for the stream of CLP=0+1 cells is performed by PCRA algorithm (Po.sub.+1) for the conventional stream of CLP=0+1 cells, together with the compensation circuit using a single register of the invention. Thus, during the traffic negotiation in which two PCR are defined in ATM networks, MPP for the streams of CLP=0 cells and CLP=0+1 cells can be solved and CLR for the stream of CLP=0 cells is guaranteed.
Method and apparatus for traffic flow control in data switches are disclosed. Emission and loss priorities of cells to be switched are translated into a single discard priority, referred to as a bandwidth priority, which has consistent meaning across different emission priorities. This translation allows simultaneous consideration of loss and emission priority in determining which cells to discard when a switch becomes congested with cell traffic. Such consideration alleviates problems that can arise if cell discard decisions are based solely on either loss priority or emission priority. The invention is particularly useful for Asynchronous Transfer Mode (ATM) switches.
There is provided a fault self-supervising system of cell processor to execute fault supervising for internal circuit in the cell processor during the in-service period while the ordinary operation of the cell processor is kept without giving any influence on the main signal cell flow in the cell processor of the ATM network. In the structure of the fault self-supervising system of cell processor, the cell such as control cell or idle cell in the ATM cell flow which is not processed in the cell processor is overwritten by the supervising cell having a combination of VPI and VCI which is not used in the cell process and it is then applied in the preceding stage of the arithmetic circuit as the supervising object an is then transferred within the arithmetic circuit, the supervising information signal CHK indicating the operating condition of the arithmetic circuit obtained as a result of the transfer is compared and collated with the expected value E, a defective circuit of arithmetic circuit is detected from matching/mismatching as a result of comparison and the supervising cell is extracted in the subsequent stage of the arithmetic circuit.
An ATM switch including a switch unit routing an ATM through an ATM connection; a controller controlling the quality of the ATM connection; and a memory for storing a quality control identifier for linking declared information concerning ATM connection quality, which is included in a call signal requesting the setup of the ATM connection, with a capability identifier for identifying the capability of the controller. The controller controls the ATM connection quality based on the capability corresponding to the capability identifier designated based on the quality control identifier obtained from the declared information. If the quality requested in the declared information is changed due to a change in an advisory promulgated by an advisory organization, a different capability identifier can be assigned by changing or adding to the setup of the quality control identifier in accordance with the updated quality.