In an integrated circuit that includes a signal path for carrying an analog signal, a test voltage from a test voltage node (V+) is applied (S2, S3) to the signal path, and the test voltage is maintained (AOA, VME) on the signal path independently of the test voltage node.
Systems and methods for digital-based, standards-compatible, testing of analog circuits embedded inside integrated circuits. In this regard, one such system can be broadly described by a test stimulus generator that transmits a binary-level test-stimulus signal into an analog circuit located inside an integrated circuit; a converter that converts an analog output signal from the analog circuit into a digital output signal; a boundary-scan register chain that transmits the digital output signal out of the integrated circuit, and a test equipment that receives the digital output signal using the IEEE 1149.1 boundary-scan standard and analyzes the digital output signal to compute one or more specifications of the analog circuit located inside the integrated circuit.
A method for accurately delivering a voltage to a circuit node of an integrated circuit having analog buses and transmission gates selectively connecting the circuit node to the buses, comprises sensing the voltage on the circuit node via a first of the buses under control of a first periodic signal; applying a first stimulus voltage to the circuit node via a second bus under control of a second periodic signal; and applying a second stimulus voltage to the circuit node under control of a third periodic signal which is inverted with respect to the second periodic signal so that the circuit node is driven alternately to the first stimulus voltage and to the second stimulus voltage.
An on-chip test bus circuit for testing a plurality of circuits and an associated method. The test bus circuit consists of a test bus and a plurality of switching circuits which selectably provide electrical connections between the respective circuits and the test bus. The plurality of switching circuits are configured to transfer an electrical charge between a node disposed within each switching circuit not selected to provide an electrical connection and a respective charge source or sink. The charge source or sink may consist of a low-impedance, substantially noise-free DC voltage or signal source. The associated method of the present invention consists of the following steps: (1) providing a test bus; (2) providing a plurality of switching circuits for selectively providing electrical connections between the respective circuits and the test bus; (3) providing one or more charge sources or sinks coupled to the respective switching circuits; (4) setting the respective switching circuit associated with a selected one of the circuits to a conducting state; (5) setting the one or more respective switching circuits associated with the one or more unselected circuits to a non-conducting state; (6) transmitting a test signal between the selected circuit and the test bus via the switching circuit in the conducting state; and (7) transferring an electrical charge between a node disposed within each of the one or more switching circuits in the non-conducting state and the respective charge source or sink. The test bus circuit and associated method are especially suitable for use with high-speed analog or mixed-signal integrated circuits.
A method and circuit for allowing direct access logic testing in integrated circuits. In one embodiment, an interface between integrated circuit core logic and integrated circuit user-defined logic is exposed, and the integrated circuit core logic and the integrated circuit user-defined logic is tested via the exposed interface. In another embodiment, an integrated circuit has logic selection circuitry connected with core logic and user-defined logic. The logic selection circuitry is used to selectively test the core logic and user-defined logic.
An on-chip test bus circuit for testing a plurality of circuits and an associated method. The test bus circuit consists of a test bus and a plurality of switching circuits which selectably provide electrical connections between the respective circuits and the test bus. The plurality of switching circuits are configured to transfer an electrical charge between a node disposed within each switching circuit not selected to provide an electrical connection and a respective charge source or sink. The charge source or sink may consist of a low-impedance, substantially noise-free DC voltage or signal source. The associated method of the present invention consists of the following steps: (1) providing a test bus; (2) providing a plurality of switching circuits for selectively providing electrical connections between the respective circuits and the test bus; (3) providing one or more charge sources or sinks coupled to the respective switching circuits; (4) setting the respective switching circuit associated with a selected one of the circuits to a conducting state; (5) setting the one or more respective switching circuits associated with the one or more unselected circuits to a non-conducting state; (6) transmitting a test signal between the selected circuit and the test bus via the switching circuit in the conducting state; and (7) transferring an electrical charge between a node disposed within each of the one or more switching circuits in the non-conducting state and the respective charge source or sink. The test bus circuit and associated method are especially suitable for use with high-speed analog or mixed-signal integrated circuits.
