Methods of forming electrically conductive interconnections and electrically interconnected substrates are described. In one implementation, a first substrate having an outer surface is provided and a layer of material is formed thereover. Openings are formed within the layer of material and conductive masses are formed within the openings. A second substrate having conductive interconnect surfaces is provided. The conductive interconnect surfaces are then contacted with the conductive masses and deformed thereby. In one aspect, the interconnect surfaces are deformed in part by portions of the layer of material proximate the conductive masses. In another aspect, the layer of material is removed and the interconnect surfaces are deformed by the conductive masses themselves.
A method and structure for coupling a semiconductor substrate (e.g., a semiconductor chip) to an organic substrate (e.g., a chip carrier). The coupling interfaces a solder member (e.g., a solder ball) to both a conductive pad on the semiconductor substrate and a conductive pad on the organic substrate. Thermal strains on the solder member during thermal cycling may be reduced by having a surface area of the pad on the semiconductor substrate exceed a surface area of the pad on the organic substrate. Thermal strains on the solder member during thermal cycling may also be reduced by having a distance from a centerline of the solder member to a closest lateral edge of the semiconductor substrate exceed about 0.25 mm.
A method and structure for coupling a semiconductor substrate (e.g., a semiconductor chip) to an organic substrate (e.g., a chip carrier). The coupling interfaces a solder member (e.g., a solder ball) to both a conductive pad on the semiconductor substrate and a conductive pad on the organic substrate. Thermal strains on the solder member during thermal cycling may be reduced by having a surface area of the pad on the semiconductor substrate exceed a surface area of the pad on the organic substrate. Thermal strains on the solder member during thermal cycling may also be reduced by having a distance from a centerline of the solder member to a closest lateral edge of the semiconductor substrate exceed about 0.25 mm.
Dielectric collars to be disposed around contact pads on a surface of a semiconductor device or another substrate and methods of fabricating and disposing the collars on semiconductor devices and other substrates. Semiconductor devices including the collars and having contact pads exposed through the collars are also disclosed. One or more of the collars are disposed around the contact pads of a semiconductor device or other substrate before or after conductive structures are secured to the contact pads. Upon connecting the semiconductor device face-down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the collars prevent the material of conductive structures protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof. The collars may be preformed structures which are attached to a surface of a semiconductor device or other substrate. Alternatively, the collars can be fabricated on the surface of the semiconductor device or other substrate. A stereolithographic method of fabricating the collars is disclosed. The stereolithographic method may include use of a machine vision system including at least one camera operably associated with a computer controlling a stereolithographic application of material so that the system may recognize the position and orientation of a semiconductor device or other substrate on which the collar is to be fabricated.
Dielectric collars are configured to be positioned laterally around contact pads of a semiconductor device or another substrate. Substrates on which the collars are positioned and that include contact pads that are exposed through the collars are also disclosed, as are methods for fabricating the collars and for positioning the collars on substrates. The collars may be positioned laterally adjacent to the contact pads of a substrate before or after conductive structures are secured to the contact pads. When the conductive structures are electrically connected to contact pads of another semiconductor device component, the collars prevent the material of the conductive structures from contacting regions of the surface of the substrate or other semiconductor device component that surround the contact pads. The collars may be preformed structures that are assembled with the substrate, or they may be formed on the substrate. A stereolithographic method of fabricating the collars is disclosed.
A method and structure to electrically and mechanically join a first a first electrically conductive pad on a first substrate to a second electrically conductive pad on a second substrate using a solder joint that includes a low-melt solder alloy composition. The second electrically conductive pad has a geometry that compels a gap size of a gap between the first substrate and the second substrate to exceed a distance between the first substrate and a surface of the second pad.
