A new control wafer configuration and method allows for the earlier detection of processing problems and resulting striations, localized high concentrations of phosphorous, in product wafers as compared to the standard control wafer configuration currently being used. By increasing the thickness of a phosphorus doped silicate glass (PSG) layer in a film stack from about 1500 .ANG. in the standard control wafer to a thickness greater than about 2500 .ANG., preferably a thickness in the range between about 3000 .ANG. to about 4000 .ANG., any localized high concentration phosphorus striations are consistently found within the PSG layer during testing. As a result, the PSG layer in the control wafer accurately represents potential defects in the product wafers. If there is a problem on the production line, the striations are detected in the control wafer before mass production of product wafers continues.

Disclosed are a capacitor of a semiconductor device and a method of fabricating the same. The capacitor includes a capacitor top electrode, a capacitor bottom electrode aligned with a bottom surface and three lateral sides of the capacitor top electrode, and a capacitor insulating layer between the capacitor top electrode and the capacitor bottom electrode.

In one embodiment, an etch stop layer and a mold layer is sequentially formed on a semiconductor substrate having an interlayer insulation layer. The interlayer insulation layer includes a conductive region formed therein. The mold layer is partially etched to expose a top surface of the etching stop layer. The exposed etching stop layer and an upper portion of the interlayer insulating layer are removed to form a first aperture part that exposes a portion of the conductive region. The conductive region exposed in the first aperture part is etched to form a second aperture part. A conductive layer for the capacitor storage node is deposited on the semiconductor substrate having the first and second aperture parts. The conductive layer provided on the mold layer is planarized to form separated capacitor storage nodes.

A method of forming capacitor over bit line storage nodes in dynamic random access memory cell includes forming a multi-layered structure having at least two silicon oxide layers as a thick molding layer, e.g., to a thickness of more than 8000 .ANG.. The at least two silicon oxide layers are disposed to have an etch speed of relatively lower-positioned silicon oxide layer to be relatively faster than that of relatively upper-positioned silicon oxide layer. Holes are then etched in the multi-layered structure, thereby reducing a width differential between the upper and lower layers.

A method of forming source/drain regions in semiconductor devices. First, a substrate having at least one gate structure is provided. Next, first, second, and third insulating spacers are successively formed over the sidewall of the gate structure. Subsequently, ion implantation is performed on the substrate on both sides of the gate structure using the third insulating spacer as a mask to form first doping regions. After the third insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the second insulating spacer as a mask to form second doping regions serving as source/drain regions with the first doping regions. Finally, after the second insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the first insulating spacer as a mask to form third doping regions, thereby preventing punchthrough.