A driving circuit reduces fall delay time, and the output timing of a driving current can be controlled highly accurately while reducing ringing during a transition of output current. Because transistor QN4 diode-connected to node ND3 and resistor element R1 are connected in parallel at driver part 30, transistor QN4 becomes conductive first as voltage V.sub.g of node ND3 falls according to input signal S.sub.in, and in accordance with a time constant based on combined resistance including its on-resistance and the resistance value of resistor element R1 voltage V.sub.g begins to drop suddenly, and when voltage V.sub.g becomes lower than the threshold voltage of transistor QN4, transistor QN4 becomes disconnected, and voltage Vg starts to drop slowly in accordance with a time constant based on the resistance value of resistor element R1, therefore the transitional characteristic in the fall of output current I.sub.H of current output transistor QN0 can be improved according to voltage V.sub.g, and the fall delay time can be reduced, so that the timing of current I.sub.H can be controlled easily.
A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor are expressed with a fixed resistance and a power supply voltage that changes with time. The power supply voltage is represented as a waveform which is a combination of two straight lines: the one indicating that the voltage, after a fixed delay of t0, increases to V1 during .DELTA.t1; and the one indicating that the voltage increases from V1 to E during .DELTA.t2 and thereafter remains at the fixed value of E. A difference in the shapes of input waveforms is adopted as a correction parameter to determine the values of .DELTA.t1, V1, and .DELTA.t2.
A method for converting a signal from a low voltage domain to a high voltage domain includes receiving an input signal in a low voltage domain, and using the input signal, controlling a first transistor having a first carrier type, a second transistor having a second carrier type different from the first carrier type, and a third transistor having the second carrier type to produce an output voltage at an output terminal. The first transistor is coupled to the output terminal and further coupled to a first voltage corresponding to a first value in a high voltage domain. The second and third transistors are coupled in series between the output terminal and a second voltage corresponding to a second value in the high voltage domain. The output voltage is selected to correspond to either the first voltage or the second voltage based upon the input signal.
Low-power and low-noise CDS (correlated double sampling) comparators for use with a CIS (CMOS image sensor) device are provided. A CDS comparator is constructed using one of various low-power inverters that provide decreased instantaneous transition currents at a logic threshold voltage. The use of such low-power inverters in CDS comparators enables a significant reduction in power consumption and noise in the CIS device, or other devices that implement such CDS comparators and/or inverters.
