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Creation of memory array bitmaps using logical to physical server



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Patent 6775796
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Document Number
US Patent 6775796
Issued Date
August 10, 2004
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Abstract
A method and system for generating memory array bitmaps is disclosed that uses the memory binary address and failing memory data bits collected during test of a chip as input and translates this input directly to physical location in physical design formats which uses memory and a logical to physical server in an electronic computer aided design system.
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Number of Claims:
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Published
August 10, 2004
Application Number
09/682,426
Filed
August 31, 2001
US Classification
714/723   365/200
Int'l Classification
G11C   29/56   (20060101)   G11C   29/44   (20060101)   G11C   29/04   (20060101)  
Examiner
Assistant Examiner
USPTO Field of Search
714/724   714/718   714/7   714/42   714/723   702/118   716/4   716/5   716/6   365/189.07   365/185.05   365/200  
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