A method and system for generating memory array bitmaps is disclosed that uses the memory binary address and failing memory data bits collected during test of a chip as input and translates this input directly to physical location in physical design formats which uses memory and a logical to physical server in an electronic computer aided design system.
A method for verifying the accuracy of bit-map memory test programs is disclosed, which employs a Focused Ion Beam (FIB) apparatus to make or break connections on one or more word lines or bit lines of the memory to be tested, causing abnormal data output from memory locations affected by such word lines or bit lines during FIB modeling. If abnormal data are also produced on the same electrical address corresponding to the physical memory address during the bit-map memory testing, that means the bit-mapping memory test program has passed the verification test, and it can be used to test other physical memory to check for any faulty address lines or memory cells; otherwise, the test program needs to be tuned through repeated correction process until the electrical addresses output from the test program match with the test pattern memory addresses.
An integrated memory includes a circuit for testing the operation of the memory, a register circuit is used for storing a bit combination, compression unit, to receive test data which have been read from the memory cells, and a memory unit to store a plurality of bits from a compressed bit fail map. Each of the bits is associated with a different address region. One of the bits registers an error data item within the associated address region. In addition, a decoder circuit is provided for receiving the compressed address and for accessing that bit in the memory unit, which is associated with a respective address region on the basis of the compressed address. A short evaluation time for a function test on the memory and flexible alignment with the individual memory size are made possible.