Methods and systems are provided for determining a total length of instruction registers. A data shift of a scan chain determines whether each device in the scan chain is an identified device. An overall length of the instruction registers of the devices is determined from an instruction shift. An actual position is determined for an identified device between each pair of sub-sequences of unidentified devices. An instruction shift of the scan chain attempts to set the respective instruction register of the identified device using one or more trial positions. If a data shift of the scan chain obtains the recognized value of the respective identification register of the identified device for one of the trial positions, then this trial position is the actual position within the overall length. The total length is determined for the instruction registers of the unidentified devices in each sub-sequence of the unidentified devices.

Methods and systems for testing devices in a scan chain are described. A first device for test and a second device for test are coupled in the scan chain. A signal selector is coupled between the first and second devices. The signal selector selects between an output signal that is output from the first device and a bypass signal that has bypassed the first device.

A device includes data input and data output pins such as found in a JTAG port and a first plurality of boundary scan cells. The device is configurable to support a secondary boundary scan cells formed from the first plurality of boundary scan cells and a second plurality of boundary scan cells in at least one external device. In one embodiment, the device includes a demultiplexer which may be configured to support a primary boundary scan chain between the JTAG port and the first plurality of boundary scan cells. The demultiplexer may also be configured to support the secondary boundary scan chain between the JTAG port and the first and the second plurality of boundary scan cells.