A method and apparatus for performing compression and/or decompression is described. In one embodiment, the present invention comprises a system having a buffer, a wavelet transform unit, and a coder. The wavelet transform unit has an input coupled to the buffer to perform a wavelet transform on pixels stored therein and to generate coefficients at an output. The coder is coupled to the wavelet transform unit to code the transformed pixels received from the buffer.
This application is a divisional of application Ser. No. 09/435,313 entitled "Reversible Embedded Wavelet System Implementation", filed Nov. 5, 1999, now U.S. Pat. No. 6,549,666, which is a divisional of application Ser. No. 08/847,074 entitled "Reversible Embedded Wavelet System Implementation", filed May 1, 1997, abandoned, which is a continuation-in-part of application Ser. No. 08/643,268, entitled "Compression/Decompression Using Reversible Embedded Wavelets", filed May 3, 1996, now U.S. Pat. No. 5,966,465, which is a continuation-in-part of application Ser. No. 08/498,036, entitled "Reversible Wavelet Transform and Embedded Codestream Manipulation", filed Jun. 30, 1995, now U.S. patent No. 5,867,602, which is a continuation-in-part of application Ser. No. 08/310,146, entitled "Apparatus for Compression Using Reversible Embedded Wavelets, filed Sep. 21, 1994, now U.S. patent No. 5,748,786.
A compute system for executing an h.264 binary decode symbol instruction including a first compute unit having a range normalization circuit and an rLPS update circuit, and operating in a first mode responsive to current rLPS, range, value and current context to generate the next normalized range and next rLPS for the current context; a second compute unit including a value update circuit, a context update circuit, and value normalization circuit responsive to current rLPS, range value and current context to obtain the output bit, normalized value and the updated current context; and a third compute unit or said first compute unit operating in a second mode including a range circuit and a next context rLPS circuit responsive to rLPS range, value and next context to obtain a next context rLPS value.
An improved programmable compute system and method for executing an H.264 binary decode symbol using only a single instruction and two compute units is achieved by providing not just one rLPS value but all four next possible rLPS values of the current context next state so that there is no delay initially while calculating the correct rLPS because all four are present and any one can be chosen; further all the parameters e.g. value, range, context, and rLPS can be served by only two available 32 bit registers by generating, locally, the MSP ninth bit, of range based on the fact that the range is normalized to a known value in the MSB.
A method of reducing spatial noise in an image. Low-pass (smoothing) filters are calculated simultaneously from three successive image rows. Three blocks (m1, m2, m3) are associated with the three successive image rows, and the blocks are processed in row-major order. This implementation is applicable to both luminance and chrominance. The number of smoothing parameters is reduced to one. The technique is applicable to both luminance and chrominance. Directional mapping is used. Extension of the technique to spatial filtering using a 5.times.5 neighborhood (using five successive image rows) is described. Embodiments of the method using the MMX instruction set are described.
Systems and methods are provided for accelerated loading of operating system and application programs upon system boot or application launch. In one aspect, a method for providing accelerated loading of an operating system includes maintaining a list of boot data used for booting a computer system, preloading the boot data upon initialization of the computer system, and servicing requests for boot data from the computer system using the preloaded boot data. The boot data may comprise program code associated with an operating system of the computer system, an application program, and a combination thereof. The boot data is retrieved from a boot device and stored in a cache memory device. The boot data is stored in a compressed format on the boot device and the preloaded boot data is decompressed prior to transmitting the preloaded boot data to the requesting system.
Systems and methods for providing accelerated data storage and retrieval utilizing lossless data compression and decompression. A data storage accelerator includes one or a plurality of high speed data compression encoders that are configured to simultaneously or sequentially losslessly compress data at a rate equivalent to or faster than the transmission rate of an input data stream. The compressed data is subsequently stored in a target memory or other storage device whose input data storage bandwidth is lower than the original input data stream bandwidth. Similarly, a data retrieval accelerator includes one or a plurality of high speed data decompression decoders that are configured to simultaneously or sequentially losslessly decompress data at a rate equivalent to or faster than the input data stream from the target memory or storage device. The decompressed data is then output at rate data that is greater than the output rate from the target memory or data storage device. The data storage and retrieval accelerator method and system may employed: in a disk storage adapter to reduce the time required to store and retrieve data from computer to disk; in conjunction with random access memory to reduce the time required to store and retrieve data from random access memory; in a display controller to reduce the time required to send display data to the display controller or processor; and/or in an input/output controller to reduce the time required to store, retrieve, or transmit data.
