Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.
CROSS-REFERENCE AND INCORPORATION BY REFERENCE OF RELATED APPLICATION
This application is a divisional of prior application Ser. No. 10/887,370, filed Jul. 6, 2004, now U.S. Pat. No. 7,131,044, issued Oct. 31, 2006;
Which is a divisional of prior application Ser. No. 09/803,599, filed Mar. 9, 2001, now U.S. Pat. No. 6,769,080, granted Jul. 27, 2004;
Which claimed priority from Provisional Application No. 60/187,972, filed Mar. 9, 2000.
This disclosure relates to and incorporates by reference TI patent specification "Low Power Testing of Very Large Circuits", application Ser. No. 09/339,734, now U.S. Pat. No. 6,519,729, and application Ser. No. 60/188,109, now U.S. Pat. No. 6,763,488.
