A semiconductor memory device including a semiconductor substrate having a trench; a dielectric film formed on the substrate; a storage node electrode formed on the dielectric film; a first insulating film formed on the storage node electrode corresponding to the trench; a gate electrode formed on the first insulating film; a second insulating film formed on the gate electrode; a gate insulating film formed on at least one the side of gate electrode; a semiconductor layer formed on the at least ...

A method of forming a narrow space using a litho-less process is disclosed. A first mask is formed on a substrate, the first mask having an edge. A spacer is then formed adjacent to the edge. A second mask is subsequently formed adjacent to the spacer. The spacer is then removed.

An integrated circuit is formed with minimal encroachment of lightly doped drain (LDD) implants partially due to barrier atoms incorporated along the migration avenues. Nitrogen is incorporated either during the LDD implant or during an anneal cycle following the LDD implant. Nitrogen helps minimize segregation and diffusion of LDD dopants placed adjacent critical channel and gate dielectric areas. Nitrogen is incorporated within a chamber while under pressure so as to minimize the temperature n...

A method of fabricating GMR devices on a CMOS substrate structure with a semiconductor device formed therein. The method includes forming a dielectric system with a planar surface having a roughness in a range of 1 .ANG. to 20 .ANG. RMS on the substrate; disposing and patterning films of giant magneto-resistive material on the planar surface so as to form a memory cell; disposing a dielectric cap on the cell so as to seal the cell and provide a barrier to subsequent operations; forming vias thro...

A method is provided for increasing the electrical activation of dopants in a semiconductor device using rapid thermal processing (RTP). An aspect of the invention includes forming a gate on a semiconductor body (12), such as a substrate (14), and implanting a dopant (28) into the semiconductor body (12) proximate the gate. The dopant (28) is partially activated using a furnace. The dopant (28) is further activated using RTP. The activation of the dopant (28) through RTP in addition to the furna...

A fuse bank for use in the laser break-link programming of an integrated circuit device. The fuse bank uses fuse elements with two ends that contain fusible regions proximate the first end and non-fusible regions proximate the second end. The fuse elements are aligned in alternately oriented parallel rows so that the first end of each fuse element is juxtaposed with the second end of any adjacent fuse element. By sequentially alternating the orientation of the fuse elements in the fuse bank, the...

A method of manufacturing an integrated circuit so as to reduce overlap between an LDD region and a gate electrode is disclosed. The method includes forming a gate electrode on a gate insulator on a semiconductor substrate, implanting a lightly-doped drain (LDD) region in the substrate using the gate electrode as a mask, removing a lateral portion of the gate electrode after implanting the LDD region, and then laterally diffusing the LDD region into the substrate such that a lateral edge of the ...

A process for fabricating a polycide SAC structure, for a MOSFET device, has been developed. This process features a polycide SAC structure, comprised of tungsten silicide on in situ doped polysilicon, using tungsten hexafluoride and dichlorosilane as reactants for deposition of tungsten silicide. A first thermal anneal treatment is performed prior to polycide patterning, supplying protection to exposed tungsten silicide sides, during the patterning procedure. A second thermal anneal treatment i...

A method is provided for forming nitride sidewall spacers self-aligned between opposed sidewall surfaces of a gate conductor and a sacrificial dielectric sidewall. In one embodiment, a transistor is formed by first CVD depositing a sacrificial across a semiconductor substrate. An opening is etched through the dielectric to the underlying substrate. A gate oxide is thermally grown across the region of the substrate exposed by the first opening. A polysilicon gate conductor is then formed within t...

An integrated circuit is fabricated by forming first source and drain regions and contact regions which electrically contact respective first source and drain regions, for first field effect transistors in an integrated circuit. Then, second source and drain regions for second field effect transistors in the integrated circuit are formed. By simultaneously forming landing pads which electrically contact the integrated circuit substrate between first spaced apart gates, and doping the integrated ...