According to a shift circuit of the present invention, two single-word length data shifters of 2.sup.n bits are arranged in parallel. Further, a selective output section is provided to selectively supply the upper 2.sup.n bits or the lower 2.sup.n bits of the double-word length data of 2.sup.n+1 bits, sign of the data and constant to an individual section in accordance with the number of the shift and the type of shift such as the shift direction, arithmetic shift or logical shift. One shifter p...

In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The ...

Recurring data sample values of a common parameter are stored in nonvolatile memory at different addresses so as to limit the maximum number of entries at any one location to less than that which results in loss of storage ability.

An electronic cash register inhibits registration of information associated with a commodity unless an operator code comprised of a plurality of digits and identifying an operator is inputted. A preset code further allows selection of the manner of indicating and printing the inputted operator code. When an operator code comprised of a plurality of digits is entered by operating a decimal keyboard or ten-key (1) and an operator code key and when a first mode is set through a mode selection key (...

An improved apparatus for forming an ordered sequence of n digital numbers from a randomly arranged set of n digital numbers is shown to be made up of: (a) n registers, each initially holding a different one of the randomly arranged set of n digital numbers; (b) a digital comparator for each adjacent pair of registers to determine whether or not the digital numbers in each adjacent pair of registers are in the ordered sequence and to interchange the digital numbers in any adjacent pair of regist...

A technique of determining the distribution of pulses along two perpendicular X-Y axes of a numerically controlled machine can be used for linear, circular, and parabolic interpolations and may be extended to computer graphics. At the initial point on the curve and at each succeeding point, a decision is made to increment the X axis, the Y axis, or both axes. This decision is based on a deviation index which is an index of closeness to the desired curve. Hardware is minimized and involves only a...

A processor and disk controller are arranged to operate with either of two types of disk drive, a drive for a five and one-fourth inch disk or a drive for an eight inch disk, and a method and apparatus are provided to test a port to detect which type disk is connected. The disk drives do not directly signal their type, and in one operation this information is derived from "drive ready", signals that are supplied separately by each disk type. In an alternative method and apparatus, this informati...

In an apparatus wherein a memory is subdivided into plural storage areas, and predetermined data are adapted to be written into respective ones of the storage areas, a method of reconfiguring the storage areas of the memory. The leading addresses of the respective storage areas and the sizes of blank portions of the respective storage areas are stored while it is discriminated whether a blank portion exists in a predetermined one of the storage areas. When there is no blank portion or substantia...

In an industrial process control system, in which a plurality of remote stations interconnected by a communications link each control and manage a plurality of input/output devices, each remote station comprises a primary data processor and a back-up data processor. The primary data processor normally exercises control over and manages the input/output devices, but, should the primary data processor fail, the back-up processor takes over management and control of the input/output devices. Period...

A data link processor (peripheral-controller), for managing data transfers to/from multiple disk drive modules, provides a hardware self-test operation to its subsystem card units when it is powered on. The data link processor momentarily disables its interfaces to the peripheral disk drives and the host computer to execute test operations and to indicate either the integrity condition or fault condition of its card units. Each card unit also has a pushbutton for self-test initiation and a local...